Datasheet

ManualsBrandsANALOG DEVICES ManualsPMICsPMIC - LDO voltage regulator Positivbe, adjustable LFCSP 16 WQ (3x3)

Triple, 200 mA, Low Noise,

High PSRR Voltage Regulator

Data Sheet

ADP322/ADP323

Rev. A

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FEATURES

Fixed (ADP322) and adjustable output (ADP323) options

Bias voltage range (VBIAS): 2.5 V to 5.5 V

LDO input voltage range (VIN1/VIN2, VIN3): 1.8 V to 5.5 V

Three 200 mA low dropout voltage regulators (LDOs)

16-lead, 3 mm × 3 mm LFCSP

Initial accuracy: ±1%

Stable with 1 μF ceramic output capacitors

No noise bypass capacitor required

3 independent logic controlled enables

Overcurrent and thermal protection

Key specifications

High PSRR

76 dB PSRR up to 1 kHz

70 dB PSRR at 10 kHz

60 dB PSRR at 100 kHz

40 dB PSRR at 1 MHz

Low output noise

29 μV rms typical output noise at V

OUT

= 1.2 V

55 μV rms typical output noise at V

OUT

= 2.8 V

Excellent transient response

Low dropout voltage: 110 mV at 200 mA load

85 μA typical ground current at no load, all LDOs enabled

100 μs fast turn-on circuit

Guaranteed 200 mA output current per regulator

−40°C to +125°C junction temperature

APPLICATIONS

Mobile phones

Digital cameras and audio devices

Portable and battery-powered equipment

Portable medical devices

Post dc-to-dc regulation

TYPICAL APPLICATION CIRCUITS

ADP322

VBIAS

VOUT1

GND

VBIAS

1µF

OFF

EN1

OFF

EN2

OFF

EN3

1µF

LDO 1

EN LD1

VBIAS

VOUT2

1µF

LDO 2

EN LD2

VOUT3

1µF

LDO 3

EN LD3

2.5V T

5.5V

VIN1/VIN2

VIN3

1µF

1.8V T

5.5V

1.8V T

5.5V

1µF

09288-001

Figure 1. Typical Application Circuit for ADP322

ADP323

VBIAS

VOUT1

GND

VBIAS

1µF

OFF

EN1

OFF

EN2

OFF

EN3

1µF

LDO 1

EN LD1

VBIAS

VOUT2

1µF

LDO 2

EN LD2

VOUT3

FB1

FB2

FB3

1µF

LDO 3

EN LD3

2.5V TO

5.5V

VIN1/VIN2

VIN3

1µF

1.8V TO

5.5V

1.8V TO

5.5V

1µF

09288-053

Figure 2. Typical Application Circuit for ADP323

GENERAL DESCRIPTION

The ADP322/ADP323 200 mA triple output LDOs combine high

PSRR, low noise, low quiescent current, and low dropout voltage

to extend the battery life of portable devices and are ideally

suited for wireless applications with demanding performance

and board space requirements.

The ADP322/ADP323 PSRR is greater than 60 dB for frequencies

as high as 100 kHz while operating with a low headroom voltage.

The ADP322/ADP323 offer much lower noise performance

than competing LDOs without the need for a noise bypass

capacitor.

The ADP322/ADP323 are available in a miniature 16-lead,

3 mm × 3 mm LFCSP package and are stable with tiny 1 µF

±30% ceramic output capacitors providing the smallest possible

board area for a wide variety of portable power needs.

The ADP322 is available in output voltage combinations ranging

from 0.8 V to 3.3 V and offers overcurrent and thermal protection

to prevent damage in adverse conditions. The APDP323

adjustable triple LDO can be configured for any output voltage

between 0.5 V and 5 V with two resistors for each output.

Summary of content (24 pages)

PAGE 1
FEATURES TYPICAL APPLICATION CIRCUITS ADP322 2.5V TO VBIAS 5.5V + 1.8V TO VIN1/VIN2 5.5V + 1µF 1µF EN1 LDO 1 VOUT1 ON + EN LD1 OFF 1µF VBIAS EN2 LDO 2 ON VOUT2 + EN LD2 OFF 1µF VBIAS 1.8V TO VIN3 5.5V + 1µF EN3 LDO 3 ON OFF VOUT3 + EN LD3 1µF GND Figure 1. Typical Application Circuit for ADP322 ADP323 2.5V TO VBIAS 5.5V + 1.8V TO VIN1/VIN2 5.
PAGE 2
ADP322/ADP323 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 15 Applications....................................................................................... 1 Applications Information .............................................................. 16 Typical Application Circuits..........................................
PAGE 3
Data Sheet ADP322/ADP323 SPECIFICATIONS VIN1/VIN2 = VIN3 = (VOUT + 0.5 V) or 1.8 V (whichever is greater), VBIAS = 2.5 V, EN1, EN2, EN3 = VBIAS, IOUT1 = IOUT2 = IOUT3 = 10 mA, CIN = COUT1 = COUT2 = COUT3 = 1 μF, and TA = 25°C, unless otherwise noted. Table 1. Parameter VOLTAGE RANGE Input Bias Voltage Range Input LDO Voltage Range CURRENT Ground Current with All Regulators On Symbol Conditions Min VBIAS VIN1/VIN2/VIN3 TJ = −40°C to +125°C TJ = −40°C to +125°C 2.5 1.
PAGE 4
ADP322/ADP323 Parameter EN INPUT EN Input Logic High EN Input Logic Low EN Input Leakage Current Data Sheet Symbol Conditions Min VIH VIL VI-LEAKAGE 2.5 V ≤ VBIAS ≤ 5.5 V 2.5 V ≤ VBIAS ≤ 5.5 V EN1 = EN2 = EN3 = VIN or GND EN1 = EN2 = EN3 = VIN or GND, TJ = −40°C to +125°C 1.2 UNDERVOLTAGE LOCKOUT Input Bias Voltage (VBIAS) Rising Input Bias Voltage (VBIAS) Falling Hysteresis OUTPUT NOISE UVLOHYS OUTNOISE POWER SUPPLY REJECTION RATIO PSRR Typ 1 2.45 V 0.1 2.
PAGE 5
Data Sheet ADP322/ADP323 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VIN1/VIN2, VIN3, VBIAS to GND VOUT1, VOUT2, FB1, FB2 to GND VOUT3, FB3 to GND EN1, EN2, EN3 to GND Storage Temperature Range Operating Junction Temperature Range Soldering Conditions Rating –0.3 V to +6.5 V –0.3 V to VIN1/VIN2 –0.3 V to VIN3 –0.3 V to +6.5 V –65°C to +150°C –40°C to +125°C JEDEC J-STD-020 Stresses above those listed under absolute maximum ratings may cause permanent damage to the device.
PAGE 6
ADP322/ADP323 Data Sheet 13 NC 14 NC 16 EN2 15 EN3 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EN1 1 12 GND 11 NC ADP322 VIN1/VIN2 3 10 VIN3 NC 4 NC 7 NC VOUT3 8 VOUT2 6 VOUT1 5 9 TOP VIEW (Not to Scale) NOTES 1. NC = NO CONNECT. 2. CONNECT EXPOSED PAD TO GROUND PLANE. 09288-002 VBIAS 2 Figure 3. ADP322 Pin Configuration Table 5. ADP322 Pin Function Descriptions Pin No.
PAGE 7
13 NC 14 NC 16 EN2 ADP322/ADP323 15 EN3 Data Sheet EN1 1 12 GND 11 NC ADP323 VIN1/VIN2 3 10 VIN3 FB1 4 FB2 7 FB3 VOUT3 8 VOUT2 6 VOUT1 5 9 TOP VIEW (Not to Scale) NOTES 1. NC = NO CONNECT. 2. CONNECT EXPOSED PAD TO GROUND PLANE. 09288-054 VBIAS 2 Figure 4. ADP323 Pin Configuration Table 6. ADP323 Pin Function Descriptions Pin No.
PAGE 8
ADP322/ADP323 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VIN1/VIN2 = VIN3 =VBIAS = 4 V, VOUT1 = 3.3 V, VOUT2 = 1.8 V, VOUT3 = 1.5 V, IOUT = 10 mA, CIN = COUT1 = COUT2 = COUT3 = 1 μF, VENX is the enable voltage, TA = 25°C, unless otherwise noted. 1.820 3.33 LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 3.32 1.810 3.31 1.805 VOUT (V) VOUT (V) LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 1.815 3.30 1.800 1.795 3.29 1.790 3.28 1.
PAGE 9
Data Sheet ADP322/ADP323 1.520 140 LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 1.500 1.495 1.490 80 60 40 LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 20 1.485 –40 –5 25 85 125 0 09288-009 1.480 TJ (°C) Figure 11. Output Voltage vs. Junction Temperature –40 –5 25 85 125 TJ (°C) Figure 14. Ground Current vs. Junction Temperature, Single Output Loaded 1.510 120 100 GROUND CURRENT (µA) 1.508 VOUT (V) 1.506 1.
PAGE 10
ADP322/ADP323 Data Sheet 350 120 100 200 150 100 LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 50 0 –40 –5 25 85 125 80 60 40 TJ (°C) LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 20 0 –40 –5 25 85 125 09288-018 BIAS CURRENT (µA) 250 09288-015 GROUND CURRENT (µA) 300 TJ (°C) Figure 20. Bias Current vs. Junction Temperature, Single Output Loaded Figure 17. Ground Current vs.
PAGE 11
Data Sheet ADP322/ADP323 0.9 300 0.6 0.5 0.4 0.3 250 200 150 100 0.2 50 0.1 –25 0 25 50 75 100 125 TEMPERATURE (°C) 0 3.10 09288-021 0 –50 Figure 23. Shutdown Current vs. Temperature at Various Input Voltages LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 VIN (V) 09288-024 0.7 GROUND CURRENT (µA) SHUTDOWN CURRENT (µA) 0.8 350 3.6 3.8 4.2 4.4 4.8 5.5 Figure 26. Ground Current vs.
PAGE 12
ADP322/ADP323 Data Sheet 160 0 120 –30 PSRR (dB) 100 80 60 –50 –60 –70 LOAD = 1mA LOAD = 5mA LOAD = 10mA LOAD = 50mA LOAD = 100mA LOAD = 200mA 1.80 –90 1.90 2.00 –100 2.10 VIN (V) –10 –20 0 –20 –30 –40 –40 PSRR (dB) –30 –60 –80 –80 –90 –100 10 –100 10 10k 100k 1M 10M 09288-028 –90 FREQUENCY (Hz) –20 200mA 100mA 10mA 1mA VRIPPLE = 50mV 1V HEADROOM 1.8V PSRR 1.2 XTALK 100 1k 10k 100k 1M 10M Figure 33. Power Supply Rejection Ratio vs.
PAGE 13
Data Sheet 70 60 ADP322/ADP323 3.3V 1.8V 1.5V ILOAD2 1 NOISE (µV rms) 50 40 30 VOUT2 2 20 0.01 0.1 1 10 100 1000 LOAD CURRENT (mA) Figure 35. Output Noise vs. Load Current and Output Voltage, VIN = 5 V CH1 200mA Ω 09288-033 0 0.001 B W B W M40µs A CH1 84mA T 10.4% Figure 38.
PAGE 14
ADP322/ADP323 Data Sheet VENx VIN VOUT1 1 1 VOUT1 2 VOUT2 VOUT3 VOUT2 3 VOUT3 4 B W B W CH2 10mV CH4 10mV B W B W M2µs A CH1 4.58V T 12% CH1 1V CH3 500mV Figure 41. Line Transient Response, VIN = 4 V to 5 V, ILOAD1 = ILOAD2 = ILOAD3 =1 mA, CH1 = VIN, CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3 B W B W CH2 500mV CH4 500mV B W B W M100µs A CH1 540mV T 10.2% Figure 42.
PAGE 15
Data Sheet ADP322/ADP323 THEORY OF OPERATION The ADP322/ADP323 triple LDO are low quiescent current, low dropout linear regulators that operate from 1.8 V to 5.5 V on VIN1/VIN2 and VIN3 and provide up to 200 mA of current from each output. Drawing a low 250 μA quiescent current (typical) at full load makes the ADP322/ADP323 ideal for battery-operated portable equipment. Shutdown current consumption is typically 100 nA.
PAGE 16
ADP322/ADP323 Data Sheet APPLICATIONS INFORMATION CAPACITOR SELECTION Input Bypass Capacitor Output Capacitor Connecting a 1 μF capacitor from VIN1/VIN2, VIN3, and VBIAS to GND reduces the circuit sensitivity to the PCB layout, especially when long input traces or high source impedance is encountered. If an output capacitance greater than 1 μF is required, the input capacitor should be increased to match it.
PAGE 17
Data Sheet ADP322/ADP323 Use Equation 1 to determine the worst-case capacitance, accounting for capacitor variation over temperature, component tolerance, and voltage. CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL) As shown in Figure 48, the ENx pin has built-in hysteresis. This prevents on/off oscillations that can occur due to noise on the ENx pin as it passes through the threshold points. (1) where: CBIAS is the effective capacitance at the operating voltage.
PAGE 18
ADP322/ADP323 Data Sheet CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION The ADP322/ADP323 are protected against damage due to excessive power dissipation by current and thermal overload protection circuits. The ADP322/ADP323 are designed to current limit when the output load reaches 300 mA (typical). When the output load exceeds 300 mA, the output voltage is reduced to maintain a constant current limit.
PAGE 19
ADP322/ADP323 140 120 120 JUNCTION TEMPERATURE, TJ (°C) 140 60 40 1000mm 2 500mm 2 100mm 2 50mm 2 JEDEC TJ MAX 20 0 0 0.2 0.4 0.6 0.8 1.0 1.2 TOTAL POWER DISSIPATION (W) Figure 51. Junction Temperature vs. Total Power Dissipation, TA = 25°C 60 40 120 JUNCTION TEMPERATURE, TJ (°C) 120 60 40 1000mm 2 500mm 2 100mm 2 50mm 2 JEDEC TJ MAX 20 0 0 0.2 0.4 0.6 0.8 TOTAL POWER DISSIPATION (W) 1.0 1.2 0.2 0.4 0.6 0.8 1.0 1.2 Figure 53. Junction Temperature vs.
PAGE 20
ADP322/ADP323 Data Sheet PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS Heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADP322/ADP323. However, as can be seen from Table 7, a point of diminishing returns is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. 09288-051 Place the input capacitor as close as possible to the VINx and GND pins.
PAGE 21
Data Sheet ADP322/ADP323 OUTLINE DIMENSIONS PIN 1 INDICATOR 3.10 3.00 SQ 2.90 0.30 0.25 0.20 0.50 BSC PIN 1 INDICATOR 16 13 1 12 1.65 1.50 SQ 1.45 EXPOSED PAD 9 0.80 0.75 0.70 SEATING PLANE 4 5 8 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 091609-A TOP VIEW 0.50 0.40 0.30 COMPLIANT TO JEDEC STANDARDS MO-229. Figure 57.
PAGE 22
ADP322/ADP323 Data Sheet NOTES Rev.
PAGE 23
Data Sheet ADP322/ADP323 NOTES Rev.