Datasheet

ADP320
Rev. A | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VIN1/VIN2, VIN3, VBIAS to GND –0.3 V to +6.5 V
VOUT1, VOUT2 to GND –0.3 V to VIN1/VIN2
VOUT3 to GND –0.3 V to VIN3
EN1, EN2, EN3 to GND –0.3 V to +6.5 V
Storage Temperature Range –65°C to +150°C
Operating Junction Temperature Range –40°C to +125°C
Soldering Conditions JEDEC J-STD-020
Stresses above those listed under absolute maximum ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination.
The ADP320 triple LDO can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temper-
ature does not guarantee that the junction temperature (T
J
)
is within the specified temperature limits. In applications
with high power dissipation and poor thermal resistance the
maximum ambient temperature may have to be derated. In
applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits.
The junction temperature (T
J
) of the device is dependent on
the ambient temperature (T
A
), the power dissipation of the
device (P
D
), and the junction-to-ambient thermal resistance of
the package (θ
JA
). Maximum junction temperature (T
J
) is
calculated from the ambient temperature (T
A
) and power dissi-
pation (P
D
) using the following formula:
T
J
= T
A
+ (P
D
× θ
JA
)
Junction-to-ambient thermal resistance (θ
JA
) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ
JA
may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θ
JA
are based on a four-layer, 4-inch × 3-inch
circuit board. Refer to JEDEC JESD 51-9 for detailed informa-
tion on the board construction. For additional information, see
the AN-617 Application Note, MicroCSP™ Wafer Level Chip
Scale Package.
Ψ
JB
is the junction to board thermal characterization parameter
with units of °C/W. Ψ
JB
of the package is based on modeling and
calculation using a 4-layer board. The JESD51-12, Guidelines
for Reporting and Using Package Thermal Information, states
that thermal characterization parameters are not the same as
thermal resistances. Ψ
JB
measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θ
JB
. Therefore, Ψ
JB
thermal paths include
convection from the top of the package as well as radiation
from the package; factors that make Ψ
JB
more useful in real-
world applications. Maximum junction temperature (T
J
) is
calculated from the board temperature (T
B
) and power
dissipation (P
D
) using the following formula
T
J
= T
B
+ (P
D
× Ψ
JB
)
Refer to JEDEC JESD51-8 and JESD51-12 for more detailed
information about Ψ
JB
.
THERMAL RESISTANCE
θ
JA
and Ψ
JB
are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4.
Package Type θ
JA
Ψ
JB
Unit
16-Lead 3 mm × 3 mm LFCSP 49.5 25.2 °C/W
ESD CAUTION