Datasheet

ADP320
Rev. A | Page 14 of 20
THEORY OF OPERATION
The ADP320 triple LDO is a low quiescent current, low dropout
linear regulator that operates from 1.8 V to 5.5 V on VIN1/VIN2
and VIN3 and provides up to 200 mA of current from each
output. Drawing a low 250 μA quiescent current (typical) at full
load makes the ADP320 triple LDO ideal for battery-operated
portable equipment. Shutdown current consumption is typically
100 nA.
Optimized for use with small 1 µF ceramic capacitors, the
ADP320 triple LDO provides excellent transient performance.
0.5V
REF
OVERCURRENT
VOUT1
VOUT2
VOUT3
VIN1/VIN2
GND
EN1
VBIAS
VIN3
EN3
EN2
0.5V
REF
OVERCURRENT
0.5V
REF
OVERCURRENT
INTERNAL BIAS
VOLTAGES/CURRENTS,
UVLO AND THERMAL
PROTECT
SHUTDOWN
VOUT1
SHUTDOWN
VOUT2
SHUTDOWN
VOUT3
09874-041
Figure 41. Internal Block Diagram
Internally, the ADP320 triple LDO consist of a reference,
three error amplifiers, three feedback voltage dividers, and
three PMOS pass transistors. Output current is delivered
via the PMOS pass device, which is controlled by the error
amplifier. The error amplifier compares the reference voltage
with the feedback voltage from the output and amplifies the
difference. If the feedback voltage is lower than the reference
voltage, the gate of the PMOS device is pulled lower, allowing
more current to flow and increasing the output voltage. If the
feedback voltage is higher than the reference voltage, the gate
of the PMOS device is pulled higher, allowing less current to
flow and decreasing the output voltage.
The ADP320 triple LDO is available in multiple output voltage
options ranging from 0.8 V to 3.3 V. The ADP320 triple LDO
uses the EN1, EN2, and EN3 enable pins to enable and disable
the VOUT1/VOUT2/VOUT3 pins under normal operating
conditions. When the enable pins are high, VOUT1/VOUT2/
VOUT3 turn on; when enable pins are low, VOUT1/VOUT2/
VOUT3 turn off. For automatic startup, the enable pins can be
tied to VBIAS.