Datasheet

Data Sheet ADP3050
Rev. C | Page 17 of 20
BOARD LAYOUT GUIDELINES
A good board layout is essential when designing a switching
regulator. The high switching currents along with parasitic
wiring inductances can generate significant voltage transients
and cause havoc in sensitive circuits. For best results, keep the
main switching path as tight as possible (keep L1, D1, C
IN
, and
C
OUT
close together) and minimize the copper area of the SWITCH
and BOOST nodes (without violating current density require-
ments) to reduce the amount of noise coupling into other
sensitive nodes.
ADP3050
GND
IN
SWITCH
C
IN
V
IN
GND
D1
C
OUT
L1
V
OUT
GND
00125-026
Figure 26. Main Switching Path
The external components should be located as close to the
ADP3050 as possible. For best thermal performance, use wide
copper traces for all IC connections, and always connect the
GND pin to a large piece of copper or ground plane. The additional
copper improves heat transfer from the IC, greatly reducing the
package thermal resistance. Further improvements of the thermal
performance can be made by using multilayer boards and using
vias to transfer heat to the other layers. A single layer board
layout is shown in Figure 27. The amount of copper used for the
input, output, and ground traces can be reduced, but were made
large to improve the thermal performance. For the 5 V and 3.3 V
versions, leave out R1 and R2; for the adjustable version, remove
the trace that shorts out R2. Route all sensitive traces and compo-
nents, such as those associated with feedback and compensation,
away from the BOOST and SWITCH traces.
TYPICAL APPLICATIONS
5 V to 3.3 V Buck (Step-Down) Regulator
The circuit in Figure 28 shows the ADP3050 in a buck
configuration. It is used to generate 3.3 V regulated output from
5 V input voltage with the following specifications:
V
IN
= 4.5 V to 5.5 V
V
OUT
= 3.3 V
I
OUT
= 0.75 A
I
RIPPLE
= 0.4 A × 0.75 A = 0.3 A
V
OUT_RIPPLE
= 50 mV
OUTPUT
GROUND
INPUT
C1
L1
C3
D1
D2
R2 R1 CC RC
C2
ADP3050
00125-027
Figure 27. Recommended Board Layout
U1
ADP3050-3.3
V
IN
C3
0.22µF
D1
1N5817
GND
5V
C1
22µF
+
C2
0.01µF
L1
22µH
V
OUT
3.3V
R1
7.5kΩ
C4
1nF
D2
1N4148
+
C5
100µF
SD
1
2
3
4
8
7
6
5
00125-028
SWITCH
BOOST
BIAS
FB
IN
GND
SD
COMP
Figure 28. 5 V to 3.3 V Buck Regulator