Datasheet

ADP3050 Data Sheet
Rev. C | Page 10 of 20
THEORY OF OPERATION
The ADP3050 is a fixed frequency, current mode buck regulator.
Current mode systems provide excellent transient response, and
are much easier to compensate than voltage mode systems (refer to
Figure 1). At the beginning of each clock cycle, the oscillator
sets the latch, turning on the power switch. The signal at the
noninverting input of the comparator is a replica of the switch
current (summed with the oscillator ramp). When this signal
reaches the appropriate level set by the output of the error amplifier,
the comparator resets the latch and turns off the power switch. In
this manner, the error amplifier sets the correct current trip
level to keep the output in regulation. If the error amplifier
output increases, more current is delivered to the output; if it
decreases, less current is delivered to the output.
The current sense amplifier provides a signal proportional to
switch current to both the comparator and to a cycle-by-cycle
current limit. If the current limit is exceeded, the latch is reset,
turning the switch off until the beginning of the next clock
cycle. The ADP3050 has a foldback current limit that reduces
the switching frequency under fault conditions to reduce stress
to the IC and to the external components.
Most of the control circuitry is biased from the 2.5 V internal
regulator. When the BIAS pin is left open, or when the voltage
at this pin is less than 2.7 V, all of the operating current for the
ADP3050 is drawn from the input supply. When the BIAS pin is
above 2.7 V, the majority of the operating current is drawn from
this pin (usually tied to the low voltage output of the regulator)
instead of from the higher voltage input supply. This can provide
substantial efficiency improvements at light load conditions,
especially for systems where the input voltage is much higher
than the output voltage.
The ADP3050 uses a special drive stage allowing the power
switch to saturate. An external diode and capacitor provide a
boosted voltage to the drive stage that is higher than the input
supply voltage. Overall efficiency is dramatically improved by
using this type of saturating drive stage.
Pulling the
SD
pin below 0.4 V puts the device in a low power
mode, shutting off all internal circuitry and reducing the supply
current to under 20 μA.
U1
ADP3050-3.3
V
IN
C3
220nF
D1
1N5818
12V
C1
22µF
+
L1
33µH
V
OUT
3.3V
R1
4kΩ
C2
1nF
+
C4
100µF
D2
1N4148
1
2
3
4
SWITCH
BOOST
BIAS
FB
IN
GND
SD
COMP
8
7
6
5
00125-024
Figure 24. Typical Application Circuit
SETTING THE OUTPUT VOLTAGE
The output of the adjustable version (ADP3050AR and
ADP3050ARZ) can be set to any voltage between 1.25 V and 12 V
by connecting a resistor divider to the FB pin as shown in
Figure 25.








−×= 1
2.1
OUT
V
R1R2
(1)
U1
ADP3050
V
IN
R1
20kΩ
R2
21.5kΩ
C
F
C3
0.22µF
D1
1N5817
GND
5V
C1
2×10µF
CERAMIC
+
C2
0.01µF
L1
22µH
V
OUT
2.5V
R
C
7.5kΩ
C
C
4.7nF
D2
1N4148
+
C4
2×22µF
CERAMIC
1
2
3
4
8
7
6
5
00125-025
SWITCH
BOOST
BIAS
FB
IN
GND
SD
COMP
Figure 25. Adjustable Output Application Circuit