Datasheet
Data Sheet ADP2442
Rev. 0 | Page 21 of 36
Table 8. Inductor Values for Various V
IN
, V
OUT
, and f
SW
Combinations
Inductor Values
f
SW
(kHz) V
IN
(V) V
OUT
(V) Min (µH) Max (µH)
300 12 3.3 22 27
300 12 5 27 33
300 24 3.3 27 33
300 24 5 39 47
300 24 12 56 68
300 36 3.3 27 33
300 36 5 39 47
300 36 12 68 82
600 12 3.3 12 15
600 12 5 15 18
600 24 3.3 15 18
600 24 5 18 22
600 24 12 27 33
600 36 3.3 15 18
600 36 5 22 27
1000
12
5
6.8
10
1000 24 5 10 12
1000 24 12 18 22
1000 36 5 12 15
To avoid inductor saturation and ensure proper operation, choose
the inductor value so that neither the saturation current nor
the maximum temperature rated current ratings are exceeded.
Inductor manufacturers specify both of these ratings in data
sheets, or the rating can be calculated as follows:
2
)(
_
L
MAXLOAD
PEAKL
I
II
∆
+=
(10)
where:
I
LOAD (MAX)
is the maximum dc load current.
ΔI
L
is the peak-to-peak inductor ripple current.
I
L_PEAK
is the peak inductor current.
Table 9. Recommended Inductors
Value (µH)
Small Inductors
(<10 mm × 10 mm)
Large Inductors
(>10 mm × 10 mm)
10 XAL4040-103ME MSS1260
18 LPS6235-183ML MSS1260
33 LPS6235-33ML MSS1260
15 XAL4040-153ME MSS1260
Output Capacitor Selection
The output capacitor selection affects both the output voltage
ripple and the loop dynamics of the regulator. The ADP2442 is
designed to operate with small ceramic output capacitors that
have low ESR and ESL; therefore, the device easily meets tight
output voltage ripple specifications. For best performance, use
X5R or X7R dielectric capacitors with a voltage rating that is
1.5 times the output voltage and avoid using Y5V and Z5U die-
lectric capacitors, which have poor temperature and dc bias
characteristics. Table 10 lists recommended capacitors from
Murata and Taiyo Yuden.
Table 10. Recommended Output Capacitors
Vendor
Capacitor Murata Taiyo Yuden
10 µF/25 V GRM32DR71E106KA12L TMK325B7106KN-TR
22 µF/25 V GRM32ER71E226KE15L TMK325B7226MM-TR
47 µF/6.3 V GCM32ER70J476KE19L JMK325B7476MM-TR
4.7 µF/50 V GRM31CR71H475KA12L UMK325B7475MMT
For acceptable maximum output voltage ripple, determine the
minimum output capacitance, C
OUT (MIN)
, as follows:
××
+×∆≅∆
)(
8
1
MINOUT
SW
LRIPPLE
Cf
ESRIV
(11)
Therefore,
)(8
)(
ESRIVf
I
C
LRIPPLE
SW
L
MINOUT
×∆−∆××
∆
≅
(12)
where:
ΔV
RIPPLE
is the allowable peak-to-peak output voltage ripple.
ΔI
L
is the inductor ripple current.
ESR is the equivalent series resistance of the capacitor.
f
SW
is the switching frequency of the regulator.
When there is a step load requirement, choose the output
capacitor value based on the value of the step load. Use the
following equation to determine the maximum acceptable
output voltage droop/overshoot caused by the step load:
∆×
×∆≅
DROOPSW
STEPOUTMINOUT
Vf
IC
3
)()(
(13)
where:
ΔI
OUT (STEP)
is the load step.
f
SW
is the switching frequency of the regulator.
ΔV
DROOP
is the maximum allowable output voltage droop/overshoot.
Select the larger of the output capacitances derived from
Equation 12 and Equation 13. When choosing the type of
ceramic capacitor for the output filter of the regulator, select a
capacitor with a nominal capacitance that is 20% to 30% larger
than the calculated value because the effective capacitance
degrades with dc voltage and temperature. Figure 60 shows the
capacitance loss resulting from the dc bias voltage for two
capacitors (X7R MLCC capacitors from Murata are shown in
Figure 60).