Datasheet

Data Sheet ADP2442
Rev. 0 | Page 15 of 36
INTERNAL BLOCK DIAGRAM
Figure 51. Internal Block Diagram
VIN
POWER STAGE
UVLO
INTERNAL LDO
VCC
BST
STATE MACHINE GATE
CONTROL LOGIC
EN
+
1.25V
FB
SS
I
SS
+
+
–
V
REF
= 0.6V
SYNC/MODE
SW
PGND
NMOS
NMOS
SLOPE
COMPENSATION/
RAMP
GENERATOR
CURRENT
LIMIT
COMPARATOR
CURRENT SENSE
AMPLIFIER
REFERENCE
CURRENT
BAND GAP
REFERENCE
PWM
COMPARATOR
FREQ
OSC
HICCUP
TIMER
COMP
THRESHOLD
PULSE SKIP
ENABLE
CLOCK
ENABLE
VCC
PULSE SKIP ENABLE
COMP
1V
PWM
HICCUP
+
+
–
AGND
115% OF
FEEDBACK
PGOOD
V
FB
86% OF
FEEDBACK
+
–
10667-043