Datasheet

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36 V,1 A, Synchronous, Step-Down, DC-to-DC

Regulator with External Clock Synchronization

Data Sheet

ADP2442

Rev. 0 Document Feedback

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FEATURES

Wide input voltage range from 4.5 V to 36 V

Low minimum on time of 50 ns typical

Maximum load current of 1 A

High efficiency of up to 94%

Adjustable output down to 0.6 V

±1% output voltage accuracy

Adjustable switching frequency from 300 kHz to 1 MHz

External synchronization from 300 kHz to 1 MHz

Pulse skip mode or forced fixed frequency mode

Precision enable input pin (EN)

Open-drain power good

Internal soft start

Overcurrent-limit protection

Shutdown current of less than 15 µA

UVLO and thermal shutdown

12-lead, 3 mm × 3 mm LFCSP package

Supported by the ADIsimPower™ tool set

APPLICATIONS

Point of load applications

Distributed power systems

Industrial control supplies

Standard rail conversion to 24 V/12 V/5 V/3.3 V

GENERAL DESCRIPTION

The ADP2442 is a constant frequency, current mode control,

synchronous, step-down, dc-to-dc regulator that is capable of

driving loads of up to 1 A with excellent line and load regulation

characteristics. The ADP2442 operates with a wide input voltage

range from 4.5 V to 36 V, which makes it ideal for regulating power

from a wide variety of sources. In addition, the ADP2442 has

very low minimum on time (50 ns) and is, therefore, suitable for

applications requiring a very high step-down ratio.

The output voltage can be adjusted from 0.6 V to 0.9 × V

High efficiency is obtained with integrated low resistance

N-channel MOSFETs for both high-side and low-side devices.

The switching frequency is adjustable from 300 kHz to 1 MHz with

an external resistor. The ADP2442 also has an accurate power-good

(PGOOD) open-drain output signal.

The ADP2442 offers the flexibility of external clock synchroni-

zation. The switching frequency can be synchronized to an external

clock, applied to the SYNC/MODE pin. The ADP2442 can also

be configured to operate in the forced fixed frequency mode for

low EMI or power saving mode to reduce the switching losses at

light load.

TYPICAL CIRCUIT CONFIGURATION

Figure 1.

The ADP2442 uses hiccup mode to protect the IC from short

circuits or from overcurrent conditions on the output. The internal

soft start limits inrush current during startup for a wide variety of

load capacitances. Other key features include input undervoltage

lockout (UVLO), thermal shutdown (TSD), and precision enable

(EN), which can also be used as a logic level shutdown input.

The A

DP2442 is available in a 3 mm × 3 mm, 12-lead LFCSP

package and is rated for a junction temperature range from

−40°C to +125°C.

Figure 2. Efficiency vs. Load Current, V

= 24 V

ADP2442

10667-001

COMP

PGOOD

FREQ

PGND

VIN

OUT

BST

AGND

VCC

COMP

BOTTOM

FREQ

TOP

BOOST

SYNC/

MODE

OUT

100

0.01 0.1

LOAD (A)

EFFICIENCY (%)

10667-002

OUT

= 12V

= 24V

PWM = 300kHz

OUT

= 5V

OUT

= 3.3V

Summary of content (36 pages)

PAGE 1
36 V,1 A, Synchronous, Step-Down, DC-to-DC Regulator with External Clock Synchronization ADP2442 Data Sheet FEATURES TYPICAL CIRCUIT CONFIGURATION C2 Wide input voltage range from 4.5 V to 36 V Low minimum on time of 50 ns typical Maximum load current of 1 A High efficiency of up to 94% Adjustable output down to 0.
PAGE 2
ADP2442 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Shutdown .................................................................... 18 Applications ....................................................................................... 1 Applications Information .............................................................. 19 General Description ............................................................
PAGE 3
Data Sheet ADP2442 SPECIFICATIONS VIN = 4.5 V to 36 V, TJ = −40°C to +125°C, unless otherwise noted. Table 1.
PAGE 4
ADP2442 Parameter POWER GOOD PGOOD High, FB Rising Threshold 5 PGOOD Low, FB Rising Threshold5 PGOOD High, FB Falling Threshold5 PGOOD Low, FB Falling Threshold5 PGOOD Delay High Leakage Current Pull-Down Resistor SYNC/MODE SYNC/MODE Input Logic High Logic Low Pulse Width Data Sheet Symbol tPGOOD IPGOOD(SRC) IPGOOD(SNK) Test Conditions/Comments Min Typ Max Unit 89 111 106 83 92 115 109 86 95 118 112 89 % % % % 50 1 0.5 10 0.7 µs µA kΩ VPGOOD = VCC FB = 0 V 2 0.
PAGE 5
Data Sheet ADP2442 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter VIN to PGND EN to AGND SW to PGND BST to PGND VCC to AGND BST to SW FREQ, PGOOD, SYNC/MODE, COMP, FB to AGND PGND to AGND Operating Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering, 10 sec) θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages based on a 4-layer standard JEDEC board. Rating −0.3 V to +40 V −0.
PAGE 6
ADP2442 Data Sheet 10 BST 11 VCC 12 AGND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS FB 1 9 VIN ADP2442 COMP 2 8 SW TOP VIEW NOTES 1. THE EXPOSED PAD SHOULD BE CONNECTED TO THE SYSTEM AGND PLANE AND PGND PLANE. 10667-003 SYNC/MODE 6 FREQ 5 7 PGND PGOOD 4 EN 3 Figure 3. Pin Configuration, Top View Table 4. Pin Function Descriptions Pin No. 1 Mnemonic FB 2 3 COMP EN 4 5 PGOOD FREQ 6 SYNC/MODE 7 PGND 8 SW 9 VIN 10 BST 11 VCC 12 AGND EP Description Feedback.
PAGE 7
Data Sheet ADP2442 TYPICAL PERFORMANCE CHARACTERISTICS EFFICIENCY IN FORCED FIXED FREQUENCY MODE 100 100 90 90 80 80 VIN = 12V VIN = 24V 60 VIN = 12V 70 EFFICIENCY (%) 50 40 60 VIN = 24V 50 40 30 30 20 20 VOUT = 3.3V fSW = 300kHz 0 0.01 0.1 LOAD (A) VOUT = 3.3V fSW = 700kHz 10 1 0 0.01 10667-104 10 0.1 LOAD (A) 1 Figure 4. Efficiency vs. Load Current, VOUT = 3.3 V, fSW = 300 kHz Figure 7. Efficiency vs. Load Current, VOUT = 3.
PAGE 8
ADP2442 Data Sheet EFFICIENCY IN PULSE SKIP MODE 100 100 VIN = 5V 90 80 80 VIN = 12V 60 70 EFFICIENCY (%) VIN = 24V 50 40 VOUT = 3.3V fSW = 300kHz COILCRAFT MSS1038 40 30 20 10 1 0 0.01 10667-004 0.1 LOAD (A) 100 VIN = 5V 90 80 EFFICIENCY (%) EFFICIENCY (%) 70 VIN = 12V 60 VIN = 24V 50 40 VOUT = 5V fSW = 300kHz COILCRAFT MSS1038 50 40 20 1 1 Figure 14. Efficiency vs.
PAGE 9
Data Sheet ADP2442 0.3 400 0 –0.1 –0.2 VOUT = 5V fSW = 700kHz SYNC = VCC, FORCED PWM MODE –0.3 0 0.2 0.4 0.6 0.8 1.0 1.2 LOAD (A) 250 fSW = 700kHz 200 150 100 VOUT = 3.3V 50 5 10 15 20 25 30 35 40 VIN (V) Figure 19. Pulse Skip (PSKIP) Threshold Load Current, VOUT = 3.3 V 1.0 0.6 0.4 TA = +25°C 0.2 TA = –40°C 0 –0.2 –0.4 TA = +125°C –0.8 –1.0 0 0.2 0.4 0.6 0.8 1.
PAGE 10
ADP2442 Data Sheet 12 1.24 1.22 VIN = 36V ENABLE RISING THRESHOLD 1.20 ENABLE VOLTAGE (V) SHUTDOWN CURENT (µA) 10 8 6 4 VIN = 4.5V 1.18 1.16 1.14 1.12 ENABLE FALLING THRESHOLD 1.10 1.08 2 50 100 150 TEMPERATURE (°C) 1.04 –50 10667-017 0 50 70 90 110 130 150 130 150 120 UVLO, RISING VIN 4.2 4.1 UVLO, FALLING VIN 4.
PAGE 11
Data Sheet ADP2442 1.80 200 1.78 175 MINIMUM OFF 1.76 ON TIME AND OFF TIME (ns) 1.74 150 1.72 CURRENT (A) 1.70 125 100 75 1.68 VIN = 36V 1.66 1.64 1.62 VIN = 4.5V 1.60 1.58 MINIMUM ON 50 1.56 1.54 25 –10 10 30 50 70 90 110 130 150 TEMPERATURE (°C) 1.50 –50 10667-024 –30 0 260 180 240 160 150 140 220 LOW-SIDE RDS(ON) (mΩ) 200 180 160 140 120 100 80 60 40 120 20 0 25 50 75 100 125 150 TEMPERATURE (°C) 0 –50 10667-027 –25 –30 Figure 29.
PAGE 12
ADP2442 Data Sheet VOUT VOUT 1 1 INDUCTOR CURRENT 4 VIN = 24V NO LOAD VOUT = 5V SYNC/MODE = VCC fSW = 700kHz 4 INDUCTOR CURRENT SW SW B W CH2 10.0V M1.00µs A CH4 CH4 500mA Ω BW T 50.40% –30mA CH1 200mV BW 10667-135 CH1 20.0mV Figure 34. PWM Mode VIN = 24 V, VOUT = 5 V, fSW = 700 kHz, Load = No Load, SYNC/MODE = VCC M2.00ms A CH1 CH2 10.0V CH4 1.00A Ω BW T 50.40% 100mV 10667-138 2 2 Figure 37.
PAGE 13
Data Sheet ADP2442 EN VOUT 3 1 VOUT VIN = 24V VOUT = 5V fSW = 700kHz PULL-UP 100kΩ VIN = 24V VOUT = 12V fSW = 300kHz 1 PGOOD LOAD 4 W M200µs A CH4 CH4 500mA Ω BW T 28.80% 260mA CH1 2.00V BW CH3 5.00V BW 10667-141 B CH1 200mV Figure 40. Load Transient Response, VIN = 24 V, VOUT = 12 V, fSW = 300 kHz, SYNC/MODE = Clock, Load Step = 500 mA CH2 2.00V M1.00ms A CH3 T 40.20% 2.80V 10667-244 2 Figure 43.
PAGE 14
ADP2442 Data Sheet VIN = 36V VOUT = 5V fSW = 700kHz LOAD = 5Ω SYNC/MODE = VCC VIN EN 3 VOUT VIN = 24V VOUT = 5V fSW = 700kHz LOAD = 5Ω SYNC/MODE = 700kHz VOUT 3 SW 1 SS 1 2 M400µs T 41.80% A CH3 6.00V CH1 2.00V BW CH3 5.00V BW Figure 46. Shutdown with VIN, PWM Mode, VIN = 36 V, VOUT = 5 V, fSW = 700 kHz, Load = 5 Ω, SYNC/MODE = VCC CH2 10.0V M1.00ms T 50.00% A CH3 2.00V 10667-150 CH2 20.0V 10667-147 2 CH1 2.00V BW CH3 10.0V BW Figure 49.
PAGE 15
Data Sheet ADP2442 INTERNAL BLOCK DIAGRAM VIN AGND VCC INTERNAL LDO BST EN UVLO + 1.25V BAND GAP REFERENCE SYNC/MODE OSC FREQ ENABLE COMP POWER STAGE CLOCK ISS PULSE SKIP ENABLE + FB PULSE SKIP ENABLE – + SS 1V NMOS STATE MACHINE GATE CONTROL LOGIC COMP THRESHOLD SW + VCC + PWM VREF = 0.
PAGE 16
ADP2442 Data Sheet THEORY OF OPERATION CONTROL ARCHITECURE The ADP2442 is based on an emulated peak current mode control architecture. The ADP2442 can operate in both fixed frequency and pulse skip modes. Fixed Frequency Mode A basic block diagram of the control architecture is shown in Figure 52. The ADP2442 can be configured in fixed frequency mode. The output voltage, VOUT, is sensed on the feedback pin, FB.
PAGE 17
Data Sheet ADP2442 ADJUSTABLE FREQUENCY EXTERNAL SYNCHRONIZATION The ADP2442 features a programmable oscillator frequency with a resistor connected between the FREQ and AGND pins. The external synchronization feature allows the switching frequency of the device to be synchronized to an external clock. The SYNC/MODE input accepts a logic level clock input ranging from 300 kHz to 1 MHz (minimum pulse width = 100 ns) and has high input impedance.
PAGE 18
ADP2442 VIN Data Sheet VIN BST SW VOUT ADP2442 R1 EN FB FREQ AGND COMP 10667-051 R2 Figure 56. Precision Enable Used as a Programmable UVLO CURRENT-LIMIT AND SHORT-CIRCUIT PROTECTION The ADP2442 has a current-limit comparator that compares the current sensed across the low-side power MOSFET to the internally set reference current.
PAGE 19
Data Sheet ADP2442 APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL Table 6. Output Voltage Selection The ADP2442 is supported by the ADIsimPower design tool set. ADIsimPower is a collection of tools that produce complete power designs optimized to a specific design goal. These tools allow the user to generate a full schematic, bill of materials, and calculate performance in minutes.
PAGE 20
ADP2442 Data Sheet 1200 Inductor Selection 1100 The high switching frequency of the ADP2442 allows for minimal output voltage ripple even when small inductors are used. Selecting the size of the inductor involves considering the trade-off between efficiency and transient response. A smaller inductor results in larger inductor current ripple, which provides excellent transient response; however, it degrades efficiency.
PAGE 21
Data Sheet ADP2442 Table 10. Recommended Output Capacitors Table 8. Inductor Values for Various VIN, VOUT, and fSW Combinations fSW (kHz) 300 300 300 300 300 300 300 300 600 600 600 600 600 600 600 1000 1000 1000 1000 VIN (V) 12 12 24 24 24 36 36 36 12 12 24 24 24 36 36 12 24 24 36 VOUT (V) 3.3 5 3.3 5 12 3.3 5 12 3.3 5 3.3 5 12 3.3 5 5 5 12 5 Inductor Values Min (µH) Max (µH) 22 27 27 33 27 33 39 47 56 68 27 33 39 47 68 82 12 15 15 18 15 18 18 22 27 33 15 18 22 27 6.
PAGE 22
ADP2442 Data Sheet LOOP COMPENSATION 30.0 The ADP2442 uses a peak current mode control architecture for excellent load and line transient response. This control architecture has two loops: an inner current loop and an external voltage loop. 19.2 22µF/25V The inner current loop senses the current in the low-side switch and controls the duty cycle to maintain the average inductor current. To ensure stable operation when the duty cycle is above 50%, slope compensation is added to the inner current loop.
PAGE 23
Data Sheet ADP2442 Correspondingly, there are three transfer functions: VCOMP (s) VREF = × g m × Z COMP (s) VOUT (s) VOUT (14) I L (s ) = GCS VCOMP (s) (15) VOUT (s) = Z FILT (s) I L (s ) (16) where: VCOMP is the comparator voltage. IL is the inductor current. gm is the transconductance of the error amplifier and equals 250 µA/V. GCS is the current sense gain and equals 2 A/V. VOUT is the output voltage of the regulator. VREF is the internal reference voltage and equals 0.6 V.
PAGE 24
ADP2442 Data Sheet DESIGN EXAMPLE Consider an application with the following specifications: Inductor Selection • • • • • • Select the inductor by using Equation 7. VIN: 24 V ± 10% VOUT: 5 V ± 1% Switching frequency: 700 kHz Load: 800 mA typical Maximum load current: 1 A Overshoot ≤ 2% under all load transient conditions L IDEAL = 3.3 × VOUT × (VIN − VOUT ) VIN × f SW LIDEAL = 3.3 × 5 V × (24 − 5) V 24 V × 700 kHz = 18.66 μH ≈ 18.
PAGE 25
Data Sheet ADP2442 In this example, the values listed in Table 12 are substituted for the variables in Equation 12 and Equation 13. Table 12. Requirements Parameter Ripple Current Voltage Ripple Voltage Droop Due to Load Transient ESR fSW Test Conditions/Comments Fixed at 0.3 A for the ADP2442 1% of VOUT 2% of VOUT Value 0.3 A 50 mV 100 mV 5 mΩ 700 kHz The calculation based on the output voltage ripple (see Equation 12) dictates that the minimum output capacitance is COUT ( MIN ) ≅ 0.
PAGE 26
ADP2442 Data Sheet TYPICAL APPLICATION CIRCUITS DESIGN EXAMPLE C3 1µF/25V BST VCC COMP VIN L1 18.3µH VOUT: 5V, 1A SW FREQ SYNC/ MODE EN C1 4.7µF/ 50V C6 0.1µF PGND C7 22µF/ 25V C8 10µF/ 25V VCC R7 50kΩ VCC PGOOD R9 132kΩ CLOCK: 700k±30% 10667-164 R2 74kΩ C2 4.7µF/ 50V ADP2442 PGOOD C10 185pF AGND FB R5 118kΩ R3 10kΩ VIN: 24V C5 10nF/50V C4 1µF/25V Figure 63. Typical Application Circuit, VIN = 24 V ± 10%, VOUT = 5 V, fSW = 700 kHz Table 14.
PAGE 27
Data Sheet ADP2442 OTHER TYPICAL CIRCUIT CONFIGURATIONS C3 1µF/25V BST VCC COMP VIN L1 33.3µH VOUT: 12V, 1A SYNC/ MODE SW FREQ EN C1 4.7µF/ 50V C6 0.1µF PGND C7 22µF/ 25V EXT R7 50kΩ VCC PGOOD R9 154kΩ CLOCK: 600k±30% 10667-165 R2 191kΩ C2 4.7µF/ 50V ADP2442 PGOOD C10 220pF AGND FB R5 121kΩ R3 10kΩ VIN: 24V C5 10nF/50V C4 1µF/25V Figure 64. Typical Application Circuit, VIN = 24 V ± 10%, VOUT = 12 V, fSW = 600 kHz Table 15.
PAGE 28
ADP2442 Data Sheet C3 1µF/25V BST VCC COMP VIN L1 18.3µH VOUT: 5V, 1A SW FREQ SYNC/ MODE EN C1 4.7µF/ 50V C6 0.1µF PGND C7 22µF/ 25V C8 22µF/ 25V EXT R7 50kΩ VCC PGOOD R9 185kΩ CLOCK: 500k±30% 10667-166 R2 74kΩ C2 4.7µF/ 50V ADP2442 PGOOD C10 270pF AGND FB R5 118kΩ R3 10kΩ VIN: 12V C5 10nF/50V C4 1µF/25V Figure 65. Typical Application Circuit, VIN = 12 V ± 10%, VOUT = 5 V, fSW = 500 kHz Table 16.
PAGE 29
Data Sheet ADP2442 C3 1µF/25V BST VCC AGND C1 4.7µF/ 50V VIN SYNC/ MODE L1 33.3µH VOUT: 3.3V, 1A SW C6 0.1µF PGND C7 47µF/ 6.3V C8 47µF/ 6.3V EXT R7 50kΩ VCC PGOOD R9 300kΩ CLOCK: 300k±30% 10667-167 R2 45kΩ EN PGOOD C10 560pF COMP C2 4.7µF/ 50V ADP2442 FREQ FB R5 91kΩ R3 10kΩ VIN: 36V C5 10nF/50V C4 1µF/25V Figure 66. Typical Application Circuit, VIN = 36 V ± 10%, VOUT = 3.3 V, fSW = 300 kHz Table 17.
PAGE 30
ADP2442 Data Sheet C3 1µF/25V BST C1 4.7µF/ 50V VIN L1 12.3µH VOUT: 3.3V, 1A FREQ SYNC/ MODE SW C6 0.1µF PGND C7 22µF/ 16V C8 10µF/ 16V EXT R7 50kΩ VCC PGOOD R9 132kΩ CLOCK: 700k±30% 10667-168 R2 45.3kΩ C2 4.7µF/ 50V COMP EN VIN: 24V C5 10nF/50V ADP2442 PGOOD C10 190pF VCC FB R5 115kΩ R3 10kΩ AGND C4 1µF/25V Figure 67. Typical Application Circuit, VIN = 24 V ± 10%, VOUT = 3.3 V, fSW = 700 kHz Table 18.
PAGE 31
Data Sheet ADP2442 POWER DISSIPATION AND THERMAL CONSIDERATIONS POWER DISSIPATION Transition Losses The efficiency of a dc-to-dc regulator is where: PIN is the input power. POUT is the output power. Transition losses occur because the N-channel MOSFET power switch cannot turn on or off instantaneously. During a switch node transition, the power switch provides all of the inductor current, and the source-to-drain voltage of the power switch is half the input, resulting in power loss.
PAGE 32
ADP2442 Data Sheet EVALUATION BOARD THERMAL PERFORMANCE 145 MAXIMUM AMBIENT TEMPERATURE (°C) TA = 25°C 45 40 35 30 25 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 IC POWER DISSIPIATION (W) Figure 68. Junction Temperature vs. Power Dissipation Based on ADP2442-EVALZ 125 105 85 65 45 25 10667-064 JUNTION TEMPERATURE (°C) 50 0 0.2 0.4 0.6 0.8 1.0 IC POWER DISSIPIATION (W) 1.2 1.4 10667-065 55 Figure 69. Maximum Ambient Temperature vs. Power Dissipation Based on ADP2442-EVALZ Rev.
PAGE 33
Data Sheet ADP2442 CIRCUIT BOARD LAYOUT RECOMMENDATIONS • • • C5 R2 FB R3 COMP VIN R6 EN R5 C10 ADP2442 VIN VIN L1 C6 C7 PGND R8 R9 NOTES 1. THICK LINE INDICATES HIGH CURRENT TRACE. Figure 70. High Current Trace CBST AGND VCC FB CIN VIN COMP VOUT FREQ PGND COUT Figure 71. PCB Top Layer Placement Rev. 0 | Page 33 of 36 VOUT SW 10667-067 • C3 VOUT 10667-066 • C4 BST • • VCC • • SYNC/ MODE • Use separate analog and power ground planes.
PAGE 34
ADP2442 Data Sheet OUTLINE DIMENSIONS 0.30 0.23 0.18 10 0.50 BSC PIN 1 INDICATOR 12 1 9 EXPOSED PAD 1.70 1.60 SQ 1.50 7 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 3 6 0.20 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 4 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-229-WEED-4. 072809-B PIN 1 INDICATOR 3.10 3.00 SQ 2.90 Figure 72.
PAGE 35
Data Sheet ADP2442 NOTES Rev.