Datasheet

ADP2441 Data Sheet
Rev. A | Page 20 of 32
The inductor value is based on V
IN(GEOMETRIC)
as follows:
SW
GEOMETRICIN
OUT
GEOMETRICIN
OUT
IDEAL
fV
VVV
L



)(
)(
)(3.3
Table 8. Inductor Values for Various V
IN
, V
OUT
, and f
SW
Combinations
Inductor Value
f
SW
(kHz) V
IN
(V) V
OUT
(V) Min (μH) Max (μH)
300 12 3.3 22 27
300 12 5 27 33
300 24 3.3 27 33
300 24 5 39 47
300 24 12 56 68
300 36 3.3 27 33
300 36 5 39 47
300 36 12 68 82
600 12 3.3 12 15
600 12 5 15 18
600 24 3.3 15 18
600 24 5 18 22
600 24 12 27 33
600 36 3.3 15 18
600 36 5 22 27
1000 12 5 6.8 10
1000 24 5 10 12
1000 24 12 18 22
1000 36 5 12 15
To avoid inductor saturation and ensure proper operation, choose
the inductor value so that neither the saturation current nor
the maximum temperature rated current ratings are exceeded.
Inductor manufacturers specify both of these ratings in data
sheets, or the rating can be calculated as follows:
2
)(
_
L
MAXLOAD
PEAKL
I
II


(10)
where:
I
LOAD(MAX)
is the maximum dc load current.
ΔI
L
is the peak-to-peak inductor ripple current.
Table 9. Recommended Inductors
Value (μH)
Small Size Inductors
(<10 mm × 10 mm)
Large Size Inductors
(>10 mm × 10 mm)
10 XAL4040-103ME MSS1260
18 LPS6235-183ML MSS1260
33 LPS6235-33ML MSS1260
15 XAL4040-153ME MSS1260
Output Capacitor Selection
The output capacitor selection affects both the output voltage
ripple and the loop dynamics of the regulator. The ADP2441 is
designed to operate with small ceramic output capacitors that
have low ESR and ESL; therefore, the device can easily meet
tight output voltage ripple specifications. For best performance,
use X5R or X7R dielectric capacitors with a voltage rating that is
1.5 times the output voltage and avoid using Y5V and Z5U
dielectric capacitors, which have poor temperature and dc bias
characteristics. Table 10 lists some recommended capacitor
from Murata and Taiyo Yuden.
For acceptable maximum output voltage ripple, determine the
minimum output capacitance, C
OUT(MIN)
, as follows:










)(
8
1
MINOUT
SW
LRIPPLE
Cf
ESRIV (11)
Therefore,
)(8
)(
ESRIVf
I
C
LRIPPLE
SW
L
MINOUT



(12)
where:
ΔV
RIPPLE
is the allowable peak-to-peak output voltage ripple.
ΔI
L
is the inductor ripple current.
ESR is the equivalent series resistance of the capacitor.
f
SW
is the switching frequency of the regulator.
If there is a step load requirement, choose the output capacitor
value based on the value of the step load. For the maximum accep-
table output voltage droop/overshoot caused by the step load,










DROOPSW
STEPOUTMINOUT
Vf
IC
3
)()(
(13)
where:
I
OUT(STEP)
is the load step.
f
SW
is the switching frequency of the regulator.
V
DROOP
is the maximum allowable output voltage droop/overshoot.
Select the largest output capacitance given by Equation 12 and
Equation 13. When choosing the type of ceramic capacitor for the
output filter of the regulator, select one with a nominal capacitance
that is 20% to 30% larger than the calculated value because the
effective capacitance degrades with dc voltage and temperature.
Figure 57 shows the capacitance loss due to the output voltage
dc bias for three X7R MLCC capacitors from Murata.