Datasheet

Data Sheet ADP2441
Rev. A | Page 15 of 32
THEORY OF OPERATION
The ADP2441 is a fixed frequency, current mode control, step-
down, synchronous switching regulator that is capable of
driving 1 A loads. The device operates with a wide input voltage
range from 4.5 V to 36 V, and its output is adjustable from 0.6 V
to 0.9 V × V
IN
. The integrated high-side N-channel power
MOSFET and the low-side N-channel power MOSFET yield
high efficiency with medium to heavy loads. Pulse skip mode is
available to improve efficiency at light loads.
The ADP2441 includes programmable features, such as soft
start, output voltage, switching frequency, and power good.
These features are programmed externally via tiny resistors and
capacitors. The ADP2441 also includes protection features, such
as UVLO with hysteresis, output short-circuit protection, and
thermal shutdown.
CONTROL ARCHITECURE
The ADP2441 is based on the emulated peak current mode
control architecture.
Fixed Frequency Mode
A basic block diagram of the control architecture is shown in
Figure 46. With medium to heavy loads, the ADP2441 operates
in the fixed switching frequency PWM mode. The output
voltage, V
OUT
, is sensed on the feedback pin, FB. An error
amplifier integrates the error between the feedback voltage and
the reference voltage (V
REF
= 0.6 V) to generate an error voltage
at the COMP pin. A current sense amplifier senses the valley
inductor current (I
L
) during the off period when the low-side
power MOSFET is on and the high-side power MOSFET is off.
An internal oscillator initiates a PWM pulse to turn off the low-
side power MOSFET and turn on the high-side power MOSFET
at a fixed switching frequency. When the high-side N-channel
power MOSFET is enabled, the valley inductor current
information is added to an emulated ramp signal, and then the
PWM comparator compares this value to the error voltage on
the COMP pin. The output of the PWM comparator modulates
the duty cycle by adjusting the trailing edge of the PWM pulse
that turns off the high-side power MOSFET and turns on the
low-side power MOSFET.
Slope compensation is programmed internally into the
emulated ramp signal and is automatically selected, depending
on the input voltage, output voltage, and switching frequency.
This prevents subharmonic oscillations for near or greater than
50% duty cycle operation. The one restriction of this feature is
that the inductor ripple current must be set between 0.2 A and
0.5 A to provide sufficient current information to the loop.
COMPARATOR
S
R
REF
DRIVER
CLOCK
COMP
V
RAMP
V
FB
V
OUT
V
IN
PWM
I
L
R
SWL
×I
L
VC
SENSE_
OUT
Q
QB
RAMP
EMULATION
BLOCK
G
CS
g
m
10581-044
Figure 46. Control Architecture Block Diagram
Pulse Skip Mode
The ADP2441 has built-in pulse skip circuitry that turns on
during light loads, switching only as necessary so that the
output voltage remains within regulation. This allows the
regulator to maintain high efficiency during operation with
light loads by reducing switching losses. The pulse skip circuitry
includes a comparator, which compares the COMP voltage to a
fixed pulse skip threshold.
COMP
CONTROL
LOGIC
ADP2441
PULSE SKIP
THRESHOLD
1VDC
10581-045
Figure 47. Pulse Skip Comparator
With light loads, the output voltage discharges at a very slow
rate (load dependent). When the output voltage is within
regulation, the device enters sleep mode and draws a very small
quiescent current. As the output voltage drops below the
regulation voltage, the COMP voltage rises above the pulse skip
threshold. The device wakes up and starts switching until the
output voltage is within regulation.
As the load increases, the settling value of the COMP voltage
increases. At a particular load, COMP settles above the pulse skip
threshold, and the part enters the fixed frequency PWM mode.
Therefore, the load current at which COMP exceeds the pulse
skip threshold is defined as the pulse skip current threshold; the
value varies with the duty cycle and the inductor ripple current.
The measured value of pulse skip threshold over V
IN
is given in
Figure 13, Figure 14, and Figure 15.