Datasheet

ADP2441 Data Sheet
Rev. A | Page 14 of 32
INTERNAL BLOCK DIAGRAM
VIN
POWER STAGE
UVLO
INTERNAL LDO
VCC
BST
STATE MACHINE GATE
CONTROL LOGIC
EN
+
1.25V
FB
I
SS
+
+
–
V
REF
= 0.6V
SS/TRK
SW
PGND
NMOS
NMOS
SLOPE
COMPENSATION/
RAMP
GENERATOR
CURRENT-LIMIT
COMPARATOR
CURRENT SENSE
AMPLIFIER
REFERENCE
CURRENT
BAND GAP
REFERENCE
PWM
COMPARATOR
FREQ
OSC
HICCUP
TIMER
COMP
THRESHOLD
PULSE SKIP
ENABLE
CLOCK
ENABLE
V
CC
COMP
1V
PWM
HICCUP
+
+
–
A
GND
115% OF
FEEDBACK
PGOOD
V
FB
86%OF
FEEDBACK
+
–
10581-043
Figure 45. Block Diagram