Datasheet

Data Sheet ADP2386
Rev. A | Page 13 of 24
SOFT START
The ADP2386 has integrated soft start circuitry to limit the output
voltage rising time and reduce inrush current at startup. The
internal soft start time is calculated using the following equation:
t
SS_INT
=
(ms)
(kHz)
1600
SW
f
A slower soft start time can be programmed by using the SS pin.
When a capacitor is connected between the SS pin and GND, an
internal current charges the capacitor to establish the soft start
ramp. The soft start time is calculated using the following equation:
t
SS_EXT
=
UPSS
SS
I
C
_
V6.0 
where:
C
SS
is the soft start capacitance.
I
SS_UP
is the soft start pull-up current (3.2 μA).
The internal error amplifier includes three positive inputs: the
internal reference voltage, the internal digital soft start voltage,
and the SS pin voltage. The error amplifier regulates the FB
voltage to the lowest of the three voltages.
If the output voltage is charged prior to turn-on, the ADP2386
prevents reverse inductor current that would discharge the output
capacitor. This function remains active until the soft start
voltage exceeds the voltage on the FB pin.
POWER GOOD
The power-good pin (PGOOD) is an active high, open-drain
output that requires an external resistor to pull it up to a voltage.
A logic high on the PGOOD pin indicates that the voltage on
the FB pin (and, therefore, the output voltage) is within regulation.
The power-good circuitry monitors the output voltage on the
FB pin and compares it to the rising and falling thresholds that
are specified in Table 1. If the rising output voltage exceeds the
target value, the PGOOD pin is held low. The PGOOD pin
continues to be held low until the falling output voltage returns
to the target value.
If the output voltage falls below the target output voltage, the
PGOOD pin is held low. The PGOOD pin continues to be held
low until the rising output voltage returns to the target value.
The power-good rising and falling thresholds are shown in
Figure 30. There is a 1024-cycle waiting period (deglitch) before
the PGOOD pin is pulled from low to high, and there is a
16-cycle waiting period (deglitch) before the PGOOD pin is
pulled from high to low.
100%
116.7%
105%
90%
95%
V
OUT
(%)
PGOOD
V
OUT
RISING
V
OUT
FALLIN
G
1024 CYCLE
DEGLITCH
16 CYCLE
DEGLITCH
1024 CYCLE
DEGLITCH
16 CYCLE
DEGLITCH
10211-130
Figure 30. PGOOD Rising and Falling Thresholds
PEAK CURRENT-LIMIT AND SHORT-CIRCUIT
PROTECTION
The ADP2386 has a peak current-limit protection circuit to
prevent current runaway. During the initial soft start, the
ADP2386 uses frequency foldback to prevent output current
runaway. The switching frequency is reduced according to the
voltage on the FB pin, which allows more time for the inductor
to discharge. The correlation between the switching frequency
and the FB pin voltage is shown in Table 5.
Table 5. FB Pin Voltage and Switching Frequency
FB Pin Voltage Switching Frequency
V
FB
≥ 0.4 V f
SW
0.4 V > V
FB
≥ 0.2 V f
SW
/2
V
FB
< 0.2 V f
SW
/4
For protection against heavy loads, the ADP2386 uses a hiccup
mode for overcurrent protection. When the inductor peak
current reaches the current-limit value, the high-side MOSFET
turns off and the low-side MOSFET turns on until the next cycle.
The overcurrent counter increments during this process. If the
overcurrent counter reaches 10, or the FB pin voltage falls to
0.4 V after the soft start, the regulator enters hiccup mode. The
high-side and low-side MOSFETs are both turned off. The
regulator remains in hiccup mode for 4096 clock cycles and then
attempts to restart. If the current-limit fault has cleared, the
regulator resumes normal operation. Otherwise, it reenters
hiccup mode.
The ADP2386 also provides a sink current limit to prevent the
low-side MOSFET from sinking a lot of current from the load.
When the voltage across the low-side MOSFET exceeds the sink
current-limit threshold, which is typically 2.5 A, the low-side
MOSFET turns off immediately for the rest of the cycle. Both high-
side and low-side MOSFETs turn off until the next clock cycle.
In some cases, the input voltage (V
PVIN
) ramp rate is too slow or
the output capacitor is too large for the output to reach regulation
during the soft start process, which causes the regulator to enter
the hiccup mode. To avoid such occurrences, use a resistor
divider at the EN pin to program the input voltage UVLO,
or use a longer soft start time.