Datasheet

Data Sheet ADP2384
Rev. 0 | Page 21 of 24
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Good printed circuit board (PCB) layout is essential for obtaining
the best performance from the ADP2384. Poor PCB layout can
degrade the output regulation, as well as the electromagnetic
interference (EMI) and electromagnetic compatibility (EMC)
performance. Figure 36 shows an example of a good PCB layout
for the ADP2384. For optimum layout, refer to the following
guidelines:
• Use separate analog ground planes and power ground
planes. Connect the ground reference of sensitive analog
circuitry, such as output voltage divider components, to
analog ground. In addition, connect the ground reference
of power components, such as input and output capacitors,
to power ground. Connect both ground planes to the exposed
GND pad of the ADP2384.
• Place the input capacitor, inductor, and output capacitor as
close as possible to the IC, and use short traces.
• Ensure that the high current loop traces are as short and as
wide as possible. Make the high current path from the input
capacitor through the inductor, the output capacitor, and the
power ground plane back to the input capacitor as short as
possible. To accomplish this, ensure that the input and output
capacitors share a common power ground plane.
• In addition, ensure that the high current path from the power
ground plane through the inductor and output capacitor
back to the power ground plane is as short as possible by
tying the PGND pins of the ADP2384 to the PGND plane
as close as possible to the input and output capacitors.
• Connect the exposed GND pad of the ADP2384 to a large,
external copper ground plane to maximize its power
dissipation capability and minimize junction temperature.
In addition, connect the exposed SW pad to the SW pins
of the ADP2384 using short, wide traces; or connect the
exposed SW pad to a large copper plane of the switching
node for high current flow.
• Place the feedback resistor divider network as close as
possible to the FB pin to prevent noise pickup. Minimize
the length of the trace that connects the top of the feedback
resistor divider to the output while keeping the trace away
from the high current traces and the switching node to
avoid noise pickup. To further reduce noise pickup, place
an analog ground plane on either side of the FB trace and
ensure that the trace is as short as possible to reduce the
parasitic capacitance pickup.
ADP2384
BST
FB
COMP
PGOOD
GND
RT
SYNC
VREG SS
SW
PGND
EN
PVIN
V
IN
C
VREG
C
IN
C
OUT
R
T
L
C
BST
V
OUT
R
TOP
R
BOT
C
SS
C
C
R
C
10725-033
Figure 35. High Current Path in the PCB Circuit
SW
SW
POWER GROUND PLANE
PVIN
VOUT
OUTPUT
CAPACITOR
INPUT
BULK
CAP
INPUT
BYPASS
CAP
INDUCTOR
SW
GND
VREG
C
VREG
C
BST
FB
COMP
PGND
GND
SW
SW
BST
PVIN
PVIN
PVIN
PGND
PGND
PGND
PGND
PGND
SW
EN
PVIN
R
TOP
PGOOD
RT
SYNC
SS
C
SS
C
C
C
CP
R
T
R
C
R
BOT
PULL UP
+
VIA
BOTTOM LAYER TRACE
ANALOG GROUND PLANE
COPPER PLANE
10725-034
Figure 36. Recommended PCB Layout