Datasheet

ADP2381 Data Sheet
Rev. 0 | Page 18 of 28
PROGRAMMING INPUT VOLTAGE UVLO
The internal voltage divider from PVIN to GND sets the default
start/stop values of the input voltage to achieve undervoltage
lockout (UVLO) performance. The default rising/falling
threshold of PVIN and UVLO are listed in Table 9. These
default values can be replaced by using an external voltage
divider to achieve a more accurate externally adjustable UVLO,
as shown in Figure 32. Lower values of the external resistors are
recommended to obtain a high accuracy UVLO threshold
because the values of the internal 320 kΩ and 125 kΩ resistors
may vary by as much as 20%.
Table 9. Default Rising/Falling Voltage Threshold
Pin Rising Threshold (V) Falling Threshold (V)
PVIN 4.28 3.92
UVLO 1.2 1.1
Figure 32. External Programmable UVLO
A 1 kΩ resistor for R2 is an appropriate choice. Use the
following equation to obtain the value of R1 for a chosen input
voltage rising threshold:
( )
V2.1
V2.1
_
R2V
R1
RISINGIN
×−
=
where V
IN_RISING
is the rising threshold of V
IN
.
The falling threshold of VIN can be determined by the
following equation:
V1.1
2
V1.1
_
+
×
=
R
R1
V
FALLINGIN
where V
IN_FALLING
is the falling threshold of V
IN
.
COMPENSATION DESIGN
The ADP2381 uses a peak current-mode control architecture
for excellent load and line transient response. For peak current-
mode control, the power stage can be simplified as a voltage
controlled current source, supplying current to the output
capacitor and load resistor. It consists of one domain pole and
one zero contributed by the output capacitor ESR.
The control to output transfer function is given by the following
equation:
P
Z
VI
COMP
OUT
VD
f
s
f
s
RA
sV
sV
sG
××
+








××
+
××==
π
π
2
1
2
1
)(
)(
)(
OUT
ESR
Z
CR
f
×××
=
π
2
1
OUT
ESR
P
CRR
f
×+××
=
)(2
1
π
where:
A
VI
= 8.7 A/V.
R is the load resistance.
C
OUT
is the output capacitance.
R
ESR
is the equivalent series resistance of the output capacitor.
The external voltage loop is compensated by a transconduct-
ance amplifier with a simple external RC network placed either
between COMP and GND or between COMP and FB, as shown
in Figure 33 and Figure 34, respectively.
Compensation Network Between COMP and GND
Figure 33 shows the simplified peak current mode control small
signal circuit with a compensation network placed between
COMP and GND.
Figure 33. Small Signal Circuit with Compensation Network Between COMP
and GND
The R
C
and C
C
compensation components contribute a zero,
and the optional C
CP
and R
C
contribute an optional pole.
The closed-loop transfer function is as follows:
)(
1
1
)( sG
s
CC
CCR
s
sCR
CC
g
RR
R
sT
VD
CPC
CPCC
CC
CPC
m
TOPBOT
BOT
V
×








×
+
××
+×
××+
×
+
−
×
+
=
Use the following design guidelines to select the R
C
, C
C
, and C
CP
compensation components:
• Determine the cross frequency, f
C
. Generally, fc is between
f
SW
/12 and f
SW
/6.
• R
C
can be calculated by
VI
m
REF
C
OUTOUT
C
AgV
fCV
R
××
××××
=
π 2
where:
V
REF
= 0.6 V.
g
m
= 500 µS.
• Place the compensation zero at the domain pole, f
P
. C
C
can
be determined by:
C
OUT
ESR
C
R
CRR
C
×+
=
)(
PVINVIN
R1
R2
UVLO
320kΩ
125kΩ
ADP2381
10209-032
R
ESR
R
+
–
g
m
R
C
C
CP
C
OUT
C
C
R
TOP
R
BOT
–
+
A
VI
V
OUT
V
COMP
V
OUT
10209-033
ADP2381
GND
COMP
FB