Datasheet

ADP2380 Data Sheet
Rev. 0 | Page 6 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
ADP2380
16
15
14
13
12
11
10
9
PVIN
UVLO
PGOOD
EN/SS
SYNC
RT
PVIN
SW
SW
LD
GND
COMP FB
PGND
VREG
BST
NOTES
1. THE EXPOSED PAD SHOULD BE SOLDERED
TO A LARGE EXTERNAL COPPER GROUND PLANE
UNDERNEATH THE IC FOR THERMAL DISSIPATION.
09939-003
Figure 3. Pin Configuration (Top View)
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1, 2 PVIN Power Input. Connect PVIN to the input power source and connect a bypass capacitor between this pin
and PGND.
3 UVLO Undervoltage Lockout Pin. An external resistor divider can be used to set the turn-on threshold.
4 PGOOD Power-Good Output (Open Drain). It is recommended that a pull-up resistor of 10 kΩ to 100 kΩ be
connected to PGOOD.
5 RT Frequency Setting. Connect a resistor between RT and GND to program the switching frequency
between 250 kHz and 1.4 MHz. If the RT pin is connected to GND, the switching frequency is set to 290 kHz.
If the RT pin is open, the switching frequency is set to 540 kHz.
6 SYNC Synchronization Input. Connect this pin to an external clock to synchronize the switching frequency
between 250 kHz and 1.4 MHz (see the Oscillator section and the Synchronization section for details).
7 EN/SS Enable (EN). When this pin voltage falls below 0.5 V, the regulator is disabled.
Soft Start (SS). This pin can also be used to set the soft start time. Connect a capacitor from SS to GND to
program the slow soft start time. If this pin is open, the regulator is enabled and uses the internal soft start.
8 COMP Error Amplifier Output. Connect an RC network from COMP to FB.
9 FB Feedback Voltage Sense Input. Connect this pin to a resistor divider from V
OUT
.
10 GND Analog Ground. Connect this pin to the ground plane.
11 PGND Power Ground. Connect this pin to the source of the synchronous N-channel MOSFET.
12 VREG Internal 8 V Regulator Output. Place a 1 µF ceramic capacitor between this pin and GND.
13 LD Low-Side Gate Driver Output. Connect this pin to the gate of the synchronous N-MOSFET.
14, 15 SW Switch Node Output. Connect this pin to the output inductor.
16 BST Supply Rail for the High-Side Gate Drive. Place a 0.1 µF ceramic capacitor between SW and BST.
17 EPAD Exposed Pad. The exposed pad should be soldered to a large external copper ground plane underneath
the IC for thermal dissipation.