Datasheet

ADP2380 Data Sheet
Rev. 0 | Page 18 of 28
PROGRAMMING INPUT VOLTAGE UVLO
The internal voltage divider from PVIN to GND sets the default
start/stop values of the input voltage to achieve undervoltage
lockout (UVLO) performance. The default rising/falling threshold
of PVIN and UVLO are listed in Table 9. For a more accurate,
externally adjustable UVLO, these default values can be replaced
by using an external voltage divider, as shown in Figure 32.
Lower values of the external resistors are recommended to obtain
a high accuracy UVLO threshold because the values of the internal
320 kΩ and 125 kΩ resistors may vary by as much as 20%.
Table 9. Default Rising/Falling Voltage Threshold
Pin Rising Threshold (V) Falling Threshold (V)
PVIN 4.28 3.92
UVLO 1.2 1.1
PVIN
V
IN
R1
R2
UVLO
320kΩ
125kΩ
ADP2380
09939-032
Figure 32. External Programmable UVLO
A 1 kΩ resistor is an appropriate choice for R2. Use the following
equation to obtain the value of R1 for a chosen input voltage
rising threshold:
( )
V2.1
V2.1
_
R2V
R1
RISINGIN
×
=
where V
IN_RISING
is the rising threshold of V
IN
.
The falling threshold of V
IN
can be determined by
V1.1
V1.1
_
+
×
=
R2
R1
V
FALLINGIN
where V
IN_FALLING
is the falling threshold of V
IN
.
COMPENSATION DESIGN
The ADP2380 uses a peak current mode control architecture
for excellent load and line transient response. For peak current
mode control, the power stage can be simplified as a voltage
controlled current source, supplying current to the output
capacitor and load resistor. It consists of one domain pole and
one zero contributed by the output capacitor ESR.
The control to output transfer function is given by
P
Z
VI
COMP
OUT
VD
f
s
f
s
RA
sV
sV
sG
××
+
××
+
××==
π
π
2
1
2
1
)(
)(
)(
OUTESR
Z
CR
f
×××
=
π
2
1
OUTESR
P
CRR
f
×+××
=
)(2
1
π
where:
A
VI
= 8.7 A/V.
R is the load resistance.
C
OUT
is the output capacitance.
R
ESR
is the equivalent series resistance of the output capacitor.
The external voltage loop is compensated by a transconductance
amplifier with a simple external RC network placed either between
COMP and GND or between COMP and FB, as shown in
Figure 33 and Figure 34, respectively.
Compensation Network Between COMP and GND
Figure 33 shows the simplified peak current mode control,
small signal circuit with a compensation network placed
between COMP and GND.
R
ESR
R
+
g
m
R
C
C
CP
C
OUT
C
C
R
TOP
R
BOT
+
A
VI
V
OUT
V
COMP
V
OUT
ADP2380
GND
COMP
FB
09939-033
Figure 33. Small Signal Circuit with Compensation Network Between COMP
and GND
The R
C
and C
C
compensation components contribute a zero,
and the optional C
CP
and R
C
contribute an optional pole.
The closed-loop transfer function is as follows:
)(
1
1
)( sG
s
CC
CCR
s
sCR
CC
g
RR
R
sT
VD
CPC
CPCC
CC
CPC
m
TOPBOT
BOT
V
×
×
+
××
+×
××+
×
+
×
+
=