Datasheet

ADP2380 Data Sheet
Rev. 0 | Page 14 of 28
If the output voltage is charged prior to turn-on, the ADP2380
prevents the low-side MOSFET from turning on, which discharges
the output voltage until the soft start voltage exceeds the voltage
on the FB pin.
When the regulator is disabled or a current fault happens, the
soft start capacitor is discharged, and the internal digital soft
start is reset to 0 V.
POWER GOOD
The power-good (PGOOD) pin is an active high, open-drain
output that requires a pull-up resistor. A logic high indicates
that the voltage at the FB pin (and, therefore, the output
voltage) is above 95% of the reference voltage and there is a
1024 cycle waiting period before PGOOD is pulled high. A logic
low indicates that the voltage at the FB pin is below 90% of the
reference voltage and there is a 16-cycle waiting period before
PGOOD is pulled low.
PEAK CURRENT-LIMIT AND SHORT-CIRCUIT
PROTECTION
The ADP2380 has a peak current-limit protection circuit to
prevent current runaway. During soft start, the ADP2380 uses
frequency foldback to prevent output current runaway. The
switching frequency is reduced according to the voltage on the
FB pin, which allows more time for the inductor to discharge.
The correlation between the switching frequency and FB pin
voltage is shown in Table 5.
Table 5. Switching Frequency and FB Pin Voltage
FB Pin Voltage Switching Frequency
V
FB
0.4 V f
SW
0.4 V > V
FB
0.2 V f
SW
/2
V
FB
< 0.2 V
f
SW
/4
For heavy load protection, the ADP2380 uses hiccup mode for
overcurrent protection. When the inductor peak current reaches
the current-limit value, the high-side MOSFET turns off and
the low-side driver turns on until the next cycle, while the
overcurrent counter increments. If the overcurrent counter
reaches 10, or the FB pin voltage falls to0.4 V after the soft
start, the regulator enters hiccup mode. The high-side MOSFET
and low-side MOSFET are both turned off. The regulator remains
in this mode for 4096 clock cycles and then attempts to restart.
If the current-limit fault is cleared, the regulator resumes
normal operation. Otherwise, it reenters hiccup mode.
The ADP2380 also provides a sink current limit to prevent the
low-side MOSFET from sinking a large amount of current from
the load. When the voltage across the low-side MOSFET exceeds
the sink current-limit threshold, which is typically 20 m V, t h e
low-side MOSFET turns off immediately for the rest of this cycle.
Both high-side and low-side MOSFETs turn off until the next
clock cycle.
In some cases, the input voltage (PVIN) ramp rate is too slow or
the output capacitor is too large to support the setting regulation
voltage during the soft start, causing the regulator to enter hiccup
mode. To avoid such cases, use a resistor divider at the UVLO
pin to program the UVLO input voltage, or use a longer soft
start time.
OVERVOLTAGE PROTECTION (OVP)
The ADP2380 provides an overvoltage protection feature to
protect the system against an output that shorts to a higher
voltage supply or the occurrence of a strong load transient.
If the feedback voltage increases to 0.7 V, the internal high-side
MOSFET and low-side driver are turned off until the voltage at FB
decreases to 0.63 V. At that time, the ADP2380 resumes normal
operation.
UNDERVOLTAGE LOCKOUT (UVLO)
The UVLO pin enable threshold is 1.2 V with 100 mV hysteresis.
The ADP2380 has an internal voltage divider that consists of
two resistors from PVIN to GND, with 320 kΩ for the high-side
resistor and 125 kΩ for the low-side resistor. An external resistor
divider from PVIN to GND can be used to override the internal
resistor divider.
THERMAL SHUTDOWN
In the event that the ADP2380 junction temperatures rise above
150°C, the thermal shutdown circuit turns off the regulator.
Extreme junction temperatures can be the result of high current
operation, poor circuit board design, and/or high ambient
temperature. A 25°C hysteresis is included so that, when thermal
shutdown occurs, the ADP2380 does not return to operation until
the on-chip temperature drops below 125°C. Upon recovery, soft
start is initiated prior to normal operation.