Datasheet

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20 V, 4 A Synchronous Step-Down

Regulator with Low-Side Driver

Data Sheet

ADP2380

Rev. 0 Document Feedback

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FEATURES

Input voltage: 4.5 V to 20 V

Integrated 44 mΩ high-side MOSFET

0.6 V ± 1% reference voltage over temperature

Continuous output current: 4 A

Programmable switching frequency: 250 kHz to 1.4 MHz

Synchronizes to external clock: 250 kHz to 1.4 MHz

180° out-of-phase synchronization

Programmable UVLO

Power-good output

External compensation

Internal soft start with external adjustable option

Startup into a precharged output

Supported by ADIsimPower design tool

APPLICATIONS

Communications infrastructure

Networking and servers

Industrial and instrumentation

Healthcare and medical

Intermediate power rail conversion

DC-to-dc point of load application

TYPICAL APPLICATIONS CIRCUIT

ADP2380

09939-001

PVIN

UVLO

PGOOD

SYNC

EN/SS

COMP

BST

VREG

PGND

GND

OSC

TOP

BOT

OUT

BST

VREG

C_EA

CP_EA

C_EA

FET

Figure 1.

100

0 1.0 2.0 3.52.51.50.5 3.0 4.0

EFFICIENCY (%)

OUTPUT CURRENT (A)

OUT

= 1.2V

OUT

= 3.3V

OUT

= 5V

09939-002

Figure 2. Efficiency vs. Output Current, V

= 12 V, f

= 250 kHz

GENERAL DESCRIPTION

The ADP2380 is a current mode control, synchronous, step-down,

dc-to-dc regulator. It integrates a 44 mΩ high-side power MOSFET

and a low-side driver to provide a high efficiency solution. The

ADP2380 runs from an input voltage of 4.5 V to 20 V and can

deliver 4 A of output current. The output voltage can be adjusted

to 0.6 V to 90% of the input voltage. The switching frequency of

the ADP2380 can be programmed from 250 kHz to 1.4 MHz or

fixed at 290 kHz or 540 kHz. The synchronization function allows

the switching frequency to be synchronized to an external clock

to minimize system noise.

External compensation and an adjustable soft start provide

design flexibility. The power-good output provides simple and

reliable power sequencing. Additional features include

programmable undervoltage lockout (UVLO), overvoltage

protection (OVP), overcurrent protection (OCP), and thermal

shutdown (TSD).

The ADP2380 operates over the −40°C to +125°C junction

temperature range and is available in a 16-lead TSSOP_EP

package.

Summary of content (28 pages)

PAGE 1
20 V, 4 A Synchronous Step-Down Regulator with Low-Side Driver ADP2380 Data Sheet FEATURES TYPICAL APPLICATIONS CIRCUIT VIN 1 2 CIN 3 4 5 ROSC 6 7 CSS 8 PVIN BST PVIN SW UVLO SW ADP2380 LD PGOOD RT VREG SYNC PGND EN/SS GND FB COMP 16 CBST 15 L VOUT 14 COUT FET 13 12 CVREG 11 10 RTOP 9 RBOT CC_EA RC_EA 09939-001 Input voltage: 4.5 V to 20 V Integrated 44 mΩ high-side MOSFET 0.
PAGE 2
ADP2380 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 15 Applications ....................................................................................... 1 Input Capacitor Selection .......................................................... 15 Typical Applications Circuit.....................................................
PAGE 3
Data Sheet ADP2380 SPECIFICATIONS VIN = 12 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 1.
PAGE 4
ADP2380 Parameter POWER GOOD (PGOOD) PGOOD Range PGOOD Deglitch Time PGOOD Leakage Current PGOOD Output Low Voltage UVLO Rising Threshold Falling Threshold THERMAL Thermal Shutdown Threshold Thermal Shutdown Hysteresis 1 2 Data Sheet Symbol Test Conditions/Comments Min FB rising threshold FB falling threshold PGOOD from low to high PGOOD from high to low VPGOOD = 5 V IPGOOD = 1 mA Typ 95 90 1024 16 0.01 125 1.06 1.2 1.1 150 25 Pin-to-pin measurement. Guaranteed by design. Rev.
PAGE 5
Data Sheet ADP2380 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter PVIN, PGOOD SW BST UVLO, FB, EN/SS, COMP, SYNC, RT VREG, LD PGND to GND Operating Junction Temperature Range Storage Temperature Range Soldering Conditions Rating −0.3 V to +22 V −1 V to +22 V VSW + 6 V −0.3 V to +6 V −0.3 V to +12 V −0.3 V to +0.3 V −40°C to +125°C −65°C to +150°C JEDEC J-STD-020 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
PAGE 6
ADP2380 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PVIN 1 16 BST PVIN 2 15 SW UVLO 3 14 SW PGOOD 4 13 LD RT 5 12 VREG SYNC 6 11 PGND EN/SS 7 10 GND COMP 8 9 TOP VIEW (Not to Scale) FB NOTES 1. THE EXPOSED PAD SHOULD BE SOLDERED TO A LARGE EXTERNAL COPPER GROUND PLANE UNDERNEATH THE IC FOR THERMAL DISSIPATION. 09939-003 ADP2380 Figure 3. Pin Configuration (Top View) Table 4. Pin Function Descriptions Pin No.
PAGE 7
Data Sheet ADP2380 TYPICAL PERFORMANCE CHARACTERISTICS 100 100 95 95 90 90 85 85 EFFICIENCY (%) 80 75 70 65 80 75 70 65 50 0 0.5 1.0 1.5 2.0 2.5 3.0 4.0 3.5 INDUCTOR: FDVE1040-6R8M MOSFET: FDS6298 55 OUTPUT CURRENT (A) 50 0 100 100 95 95 90 90 85 85 EFFICIENCY (%) EFFICIENCY (%) 1.5 2.0 2.5 3.0 80 75 70 VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V VOUT = 5V 75 70 VOUT = 1.0V VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V 55 60 50 0 0.5 1.0 1.5 2.0 2.
PAGE 8
ADP2380 4.5 Data Sheet 1.30 RISING FALLING 4.4 RISING FALLING UVLO PIN THRESHOLD (V) PVIN UVLO THRESHOLD (V) 1.25 4.3 4.2 4.1 4.0 3.9 3.8 1.20 1.15 1.10 1.05 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 1.00 –40 09939-010 3.6 –40 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 10. PVIN UVLO Threshold vs. Temperature Figure 13. UVLO Pin Threshold vs. Temperature 3.3 606 604 3.2 FEEDBACK VOLTAGE (mV) SS PULL-UP CURRENT (μA) –20 09939-011 3.7 3.1 3.0 602 600 598 2.
PAGE 9
Data Sheet ADP2380 8.0 PEAK CURRENT-LIMIT THRESHOLD (A) 70 50 40 20 –40 –20 0 20 40 60 80 100 7.0 6.5 6.0 5.5 5.0 –40 09939-016 30 7.5 120 TEMPERATURE (°C) –20 0 20 40 60 80 100 09939-019 MOSFET RESISTOR (mΩ) 60 120 TEMPERATURE (°C) Figure 16. MOSFET RDSON vs. Temperature Figure 19. Current-Limit Threshold vs. Temperature SW SW 1 1 LD LD 2 CH2 5.00V M20.0ns T 50.00% A CH2 5.50V CH1 5.00V Figure 17. Low-Side Driver Rising Edge Waveform, CDL = 2.2 nF CH2 5.
PAGE 10
ADP2380 Data Sheet SYNC EN/SS 3 3 VOUT 1 2 SW PGOOD 2 IL 4.40V CH3 5.00V BW Figure 22. Precharged Output CH2 10.0V M1.00µs T 50.40% A CH2 7.40V 09939-025 A CH2 13.8V 09939-026 CH1 2.00V BW CH2 5.00V M2.00ms CH3 5.00V BW CH4 2.00A Ω BW T 60.40% 09939-022 4 Figure 25. External Synchronization VOUT (AC) VOUT (AC) 1 1 VIN SW IOUT 3 2 CH1 100mV B M200µs W CH4 2.00A Ω BW T 70.40% A CH4 2.96A 09939-023 4 Figure 23.
PAGE 11
ADP2380 5 4 4 3 2 1 0 45 VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V VOUT = 5V 55 3 2 1 65 75 85 95 105 AMBIENT TEMPERATURE (°C) 0 45 VOUT = 1V VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V VOUT = 5V 55 65 75 85 95 105 AMBIENT TEMPERATURE (°C) Figure 28. Load Current vs. Ambient Temperature, VIN = 12 V, fSW = 500 kHz Figure 29. Load Current vs. Ambient Temperature, VIN = 12 V, fSW = 250 kHz Rev.
PAGE 12
ADP2380 Data Sheet FUNCTIONAL BLOCK DIAGRAM VREG ADP2380 CLK RT BIAS AND DRIVER REGULATOR OSCILLATOR SYNC PVIN SLOPE RAMP UVLO PVIN 320kΩ UVLO BOOST REGULATOR + 125kΩ 1.2V + ACS – – SLOPE RAMP Σ IMAX + OCP – HICCUP MODE COMP BST ISS 0.6V + EN/SS + FB – 0.7V + CMP – AMP – NFET DRIVER SW CONTROL LOGIC AND MOSFET DRIVER WITH ANTICROSS PROTECTION OVP + VREG CLK 0.54V LD DRIVER – PGND + PGOOD GND + Figure 30. Functional Block Diagram Rev.
PAGE 13
Data Sheet ADP2380 THEORY OF OPERATION CONTROL SCHEME The ADP2380 uses fixed frequency, peak current mode PWM control architecture. At the start of each oscillator cycle, the high-side N-MOSFET is turned on, putting a positive voltage across the inductor. Current in the inductor increases until the current sense signal crosses the peak inductor current threshold that turns off the high-side N-MOSFET and turns on the low-side N-MOSFET.
PAGE 14
ADP2380 Data Sheet If the output voltage is charged prior to turn-on, the ADP2380 prevents the low-side MOSFET from turning on, which discharges the output voltage until the soft start voltage exceeds the voltage on the FB pin. When the regulator is disabled or a current fault happens, the soft start capacitor is discharged, and the internal digital soft start is reset to 0 V. POWER GOOD The power-good (PGOOD) pin is an active high, open-drain output that requires a pull-up resistor.
PAGE 15
Data Sheet ADP2380 APPLICATIONS INFORMATION The maximum output voltage for a given input voltage and switching frequency is constrained by the minimum off time and the maximum duty cycle. The minimum off time is typically 200 ns, and the maximum duty cycle of the ADP2380 is typically 90%. INPUT CAPACITOR SELECTION The input decoupling capacitor is used to attenuate high frequency noise on the input. This capacitor should be a ceramic capacitor in the range of 10 µF to 47 µF.
PAGE 16
ADP2380 Data Sheet For a duty cycle that is larger than 50%, the minimum inductor value is determined by the following equation: L(Minimum) = VOUT × (1 − D ) 2 × f SW The inductor peak current is calculated using the following equation: The saturation current of the inductor must be larger than the peak inductor current.
PAGE 17
Data Sheet ADP2380 OUTPUT CAPACITOR SELECTION Select the largest output capacitance given by COUT_UV, COUT_OV, and COUT_RIPPLE to meet both load transient and output ripple performance. The output capacitor selection affects both the output ripple voltage and the loop dynamics of the regulator.
PAGE 18
ADP2380 Data Sheet PROGRAMMING INPUT VOLTAGE UVLO The control to output transfer function is given by The internal voltage divider from PVIN to GND sets the default start/stop values of the input voltage to achieve undervoltage lockout (UVLO) performance. The default rising/falling threshold of PVIN and UVLO are listed in Table 9. For a more accurate, externally adjustable UVLO, these default values can be replaced by using an external voltage divider, as shown in Figure 32.
PAGE 19
Data Sheet ADP2380 Use the following design guidelines to select the RC, CC, and CCP compensation components: • • Determine the cross frequency, fC. Generally, fc is between fSW/12 and fSW/6. RC can be calculated by RC = • RC C C = RC _ EAC C _ EA − CCP is optional, and it can be used to cancel the zero caused by the ESR of the output capacitors.
PAGE 20
ADP2380 Data Sheet DESIGN EXAMPLE This section provides the procedures for selecting the external components based on the example specifications listed in Table 10. The schematic of this design example is shown in Figure 36. Calculate the rms current flowing through the inductor using the following equation: I RMS = I OUT 2 + Table 10.
PAGE 21
Data Sheet ADP2380 LOW-SIDE MOSFET SELECTION This results in the following: RC_EA = 52.3 kΩ. CC_EA = 1055 pF. CCP_EA = 2.45 pF. A low RDSON N-channel MOSFET is chosen as a high efficiency solution. The breakdown voltage of the MOSFET must be higher than 1.2 × VIN, and the drain current must be larger than 1.2 × ILIMIT. Choose the standard values for RC_EA = 49.9 kΩ, CC_EA = 1000 pF, and CCP_EA = 2.2 pF. It is recommended to use a 30 V, N-channel MOSFET, such as the FDS6298 from Fairchild.
PAGE 22
ADP2380 Data Sheet RECOMMENDED EXTERNAL COMPONENTS Table 11. Recommended External Components for Typical Applications with Compensation Network Between COMP and GND Pins, 4 A Output Current fSW (kHz) 250 500 1000 1 VIN (V) 12 12 12 12 12 12 12 5 5 5 5 5 5 12 12 12 12 12 12 5 5 5 5 5 5 12 12 12 12 5 5 5 5 5 5 VOUT (V) 1 1.2 1.5 1.8 2.5 3.3 5 1 1.2 1.5 1.8 2.5 3.3 1.2 1.5 1.8 2.5 3.3 5 1 1.2 1.5 1.8 2.5 3.3 1.8 2.5 3.3 5 1 1.2 1.5 1.8 2.5 3.3 L (µH) 3.3 3.3 4.7 4.7 6.8 6.8 10 3.3 3.3 3.3 3.3 4.7 3.
PAGE 23
Data Sheet ADP2380 Table 12. Recommended External Components for Typical Applications with Compensation Network Between COMP and FB Pins, 4 A Output Current fSW (kHz) 250 500 1000 1 VIN (V) 12 12 12 12 12 12 12 5 5 5 5 5 5 12 12 12 12 12 12 5 5 5 5 5 5 12 12 12 12 5 5 5 5 5 5 VOUT (V) 1 1.2 1.5 1.8 2.5 3.3 5 1 1.2 1.5 1.8 2.5 3.3 1.2 1.5 1.8 2.5 3.3 5 1 1.2 1.5 1.8 2.5 3.3 1.8 2.5 3.3 5 1 1.2 1.5 1.8 2.5 3.3 L (µH) 3.3 3.3 4.7 4.7 6.8 6.8 10 3.3 3.3 3.3 3.3 4.7 3.3 2.2 2.2 2.2 3.3 4.7 4.7 1.5 1.5 2.
PAGE 24
ADP2380 Data Sheet CIRCUIT BOARD LAYOUT RECOMMENDATIONS Good circuit board layout is essential for obtaining the best performance from the ADP2380. Poor printed circuit board (PCB) layout degrades the output regulation as well as the electromagnetic interface (EMI) and electromagnetic compatibility (EMC) performance. Figure 38 shows a PCB layout example. For optimum layout, use the following guidelines: • • • Use separate analog ground and power ground planes.
PAGE 25
Data Sheet ADP2380 POWER GROUND PLANE VIN + INPUT BULK CAP OUTPUT CAPACITOR INPUT BYPASS CAP PULL UP LOW-SIDE MOSFET PVIN BST PVIN SW UVLO SW PGOOD INDUCTOR SW VOUT LD RT VREG SYNC PGND EN/SS GND COMP FB CC_EA CBST CVREG RC_EA RTOP CSS ROSC RBOT CCP_EA ANALOG GROUND PLANE 09939-038 VIA BOTTOM LAYER TRACE COPPER PLANE Figure 38. Recommended PCB Layout Rev.
PAGE 26
ADP2380 Data Sheet TYPICAL APPLICATIONS CIRCUITS VIN = 12V 1 CIN 10µF 25V 2 3 4 ROSC 100kΩ 5 6 7 CSS 22nF 8 PVIN BST PVIN SW UVLO SW ADP2380 LD PGOOD VREG RT SYNC PGND EN/SS GND COMP FB 16 L1 2.2µH CBST 0.1µF 15 VOUT = 1.2V COUT 470µF 6.3V 14 M1 FDS6298 13 12 11 CVREG 1µF RTOP 10kΩ 1% 10 9 RBOT 10kΩ 1% RC 68kΩ CCP 68pF 09939-039 CC 2.2nF Figure 39. Compensation Network Between COMP and GND, VIN = 12 V, VOUT = 1.2 V, IOUT = 4 A, fSW = 500 kHz CIN 10µF 25V 1 R1 7.
PAGE 27
Data Sheet ADP2380 OUTLINE DIMENSIONS 5.10 5.00 4.90 2.31 1.75 9 16 16 9 4.50 4.40 4.30 1 2.46 1.75 EXPOSED PAD 6.40 BSC 8 8 1 PIN 1 INDICATOR BOTTOM VIEW TOP VIEW 0.95 0.90 0.85 SEATING PLANE 0.30 0.19 0.65 BSC 0.20 0.09 0.25 8° 0.15 MAX 0° 0.05 MIN COPLANARITY 0.076 0.70 0.60 0.50 COMPLIANT TO JEDEC STANDARDS MO-153-ABT 08-03-2010-A 1.10 MAX FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Figure 42.