Datasheet

Data Sheet ADP2323
Rev. A | Page 21 of 32
where:
ΔV
OUT_RIPPLE
is the allowable output voltage ripple.
R
ESR
is the equivalent series resistance of the output capacitor.
Select the largest output capacitance given by C
OUT_UV
, C
OUT_OV
,
and C
OUT_RIPPLE
to meet both load transient and output ripple
performance.
The selected output capacitor voltage rating must be greater
than the output voltage. The minimum rms current rating of
the output capacitor is determined by the following equation:
12
_
L
rmsC
I
I
OUT
∆
=
LOW-SIDE POWER DEVICE SELECTION
The ADP2323 has integrated low-side MOSFET drivers, which
can drive the low-side N-channel MOSFETs (NFETs). The
selection of the low-side N-channel MOSFET affects the dc-to-
dc regulator performance.
The selected MOSFET must meet the following requirements:
• Drain source voltage (V
DS
) must be higher than 1.2 × V
IN
.
• Drain current (I
D
) must be greater than the 1.2 × I
LIMIT_MAX
,
where I
LIMIT_MAX
is the selected maximum current-limit
threshold.
The ADP2323 low-side gate drive voltage is 5 V. Make sure that
the selected MOSFET can be fully turned on at 5 V.
Total gate charge (Qg at 5 V) must be less than 30 nC. Lower Qg
characteristics constitute higher efficiency.
When the high-side MOSFET is turned off, the low-side
MOSFET carries the inductor current. For low duty cycle
applications, the low-side MOSFET carries the current for most
of the period. To achieve higher efficiency, it is important to
select a low on-resistance MOSFET. The power conduction loss
for the low-side MOSFET can be calculated using the following
equation:
P
FET_LOW
= I
OUT
2
× R
DSON
× (1 − D)
where R
DSON
is the on resistance of the low-side MOSFET.
Make sure that the MOSFET can handle the thermal dissipation
due to the power loss.
In some cases, efficiency is not critical for the system; therefore,
the diode can be selected as the low-side power device. The
average current of the diode can be calculated using the
following equation:
I
DIODE (AVG)
= (1 − D) × I
OUT
The reverse breakdown voltage rating of the diode must be
greater than the input voltage with an appropriate margin to
allow for ringing, which may be present at the SWx node. A
Schottky diode is recommended because it has low forward
voltage drop and fast switching speed.
If a diode is used for the low-side device, the ADP2323 must
enable the PFM mode by connecting the MODE pin to ground.
Table 10. Recommended MOSFETs
Vendor Part No. V
DS
I
D
R
DSON
Qg
Fairchild FDS8880 30 V 10.7 A 12 mΩ 12 nC
Fairchild FDMS7578 25 V 14 A 8 mΩ 8 nC
Fairchild FDS6898A 20 V 9.4 A 14 mΩ 16 nC
Vishay Si4804CDY 30 V 7.9 A 27 mΩ 7 nC
Vishay SiA430DJ 20 V 10.8 A 18.5 mΩ 5.3 nC
AOS AON7402 30 V 39 A 15 mΩ 7.1 nC
AOS AO4884L 40 V 10 A 16 mΩ 13.6 nC
PROGRAMMING UVLO INPUT
The precision enable input can be used to program the UVLO
threshold and hysteresis of the input voltage as shown in Figure 46.
ENx
1.2V
EN CMP
4µA1µA
PVINx
R
TOP_EN
R
BOT_EN
09357-048
Figure 46. Programming UVLO Input
Use the following equation to calculate R
TOP_EN
and R
BOT_EN
:
μA1V2.1μA5V1.1
V2.1V1.1
__
_
×−×
×−×
=
FALLINGINRISINGIN
ENTOP
VV
R
V2.1μ5
V2.1
_
_
_
_
−Α×−
×
=
ENTOP
RISINGIN
ENTOP
ENBOT
RV
R
R
where:
V
IN_RISING
is the V
IN
rising threshold.
V
IN_FALLING
is the V
IN
falling threshold.
COMPENSATION COMPONENTS DESIGN
For peak current-mode control, the power stage can be
simplified as a voltage controlled current source supplying
current to the output capacitor and load resistor. It is composed of
one domain pole and a zero contributed by the output capacitor
ESR. The control-to-output transfer function is shown in the
following equations:








×π×
+








×π×
+
××==
p
z
VI
COMP
OUT
vd
f
s
f
s
RA
sV
sV
sG
2
1
2
1
)(
)(
)(
OUT
ESR
z
CR
f
××π×
=
2
1
( )
OUT
ESR
p
CRR
f
×+×π×
=
2
1
where:
A
VI
= 5 A/V
R is the load resistance.
C
OUT
is the output capacitance.