Datasheet

Data Sheet ADP222/ADP223/ADP224/ADP225
Rev. D | Page 19 of 24
ENABLE FEATURE
The ADP222/ADP223/ADP224/ADP225 use the ENx pins to
enable and disable the VOUTx pins under normal operating
conditions. Figure 67 shows a rising voltage on ENx crossing
the active threshold, where V
OUTx
turns on. When a falling
voltage on ENx crosses the inactive threshold, V
OUTx
turns off.
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
OUTPUT VOLTAGE (V)
ENABLE VOLTAGE (V)
V
IN
= 5.5V
09376-045
Figure 67. Typical ENx Pin Operation, V
IN
= 5.5 V
As shown in Figure 67, the ENx pins have built-in hysteresis.
This prevents on/off oscillations that can occur due to noise on
the ENx pins as it passes through the threshold points.
The active/inactive thresholds of the ENx pins are derived from
the VIN voltage. Therefore, these thresholds vary with changing
input voltage. Figure 68 shows typical ENx active/inactive thresholds
when the input voltage varies from 2.5 V to 5.5 V.
0
0.2
0.4
0.6
0.8
1.0
1.2
2.3
2.7 3.1 3.5 3.9 4.3 4.7 5.1
5.5
ENABLE THRESHOLDS (V)
V
IN
(V)
ENx FALL
ENx RISE
09376-046
Figure 68. Typical Enable Thresholds vs. Input Voltage
The ADP222/ADP223/ADP224/ADP225 use an internal soft
start to limit the inrush current when the output is enabled. The
start-up time for the 2.8 V option is approximately 240 µs from
the time the ENx active threshold is crossed to when the output
reaches 90% of its final value. The start-up time is somewhat
dependent on the output voltage setting and increases slightly as
the output voltage increases.
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
100 200 300 400
500
600
700
800
900
1000
OUTPUT VOLTAGE (V)
TIME (µs)
ENx
3.3V
2.8V
1.8V
1.2V
09376-047
Figure 69. Typical Start-Up Time
PARALLELING OUTPUTS TO INCREASE OUTPUT
CURRENT
The ADP223/ADP225 use a single band gap to generate the
reference voltage for each LDO. The reference voltages are
trimmed to plus or minus a couple of millivolts of each other.
This allows paralleling of the LDOs to increase the output
current to 600 mA. The adjust pins of each LDO are tied
together and a single output voltage divider sets the output
voltage. Even though the output voltage of each LDO is slightly
different, at high load currents, the resistance of the package
and the board layout absorbs the difference. Figure 70 shows
the schematic of a typical application where the LDO outputs
are paralleled.
EN1
VOUT1
VIN
EN2
GND
6
4
3
2
ADJ2 VOUT2
1 8
5
7
ADJ1
R1
R2
ON
OFF
V
IN
= 3.3V
+
C1
1µF
+
C2
1µF
VOUT2 = 2.8V
09376-053
Figure 70. Paralleling Outputs for Higher Output Current
QUICK OUTPUT DISCHARGE (QOD) FUNCTION
The ADP224/ADP225 include an output discharge resistor to
force the voltage on each output to zero when the respective
LDO is disabled. This ensures that the outputs of the LDOs are
always in a well-defined state, regardless if it is enabled or not.
The ADP222/ADP223 do not include the output discharge
function. Figure 71 compares the turn-off time of a 3.3 V output
LDO with and without the QOD function. Both LDOs have a
1 kΩ resistor connected to each output. The LDO with the
QOD function discharges the output to 0 V in less than 1 ms,
whereas the 1 kΩ load takes over 5 ms to do the same.