Datasheet

ADP2147
Rev. 0 | Page 11 of 16
THEORY OF OPERATION
I
LIMIT
LOW
CURRENT
PSM
COMP
SOFT START
UNDERVOLTAGE
LOCKOUT
THERMAL
SHUTDOWN
DRIVER
AND
ANTISHOOT-
THROUGH
OSCILLATOR
PWM
COMP
GM ERROR
AMP
ADP2147
VOUT
VSEL
GND
EN
SW
VIN
09885-027
PWM/
PSM
CONTROL
Figure 33. Functional Block Diagram
The ADP2147 is a step-down dc-to-dc regulator that uses a
fixed frequency and high speed current-mode architecture.
The high switching frequency and tiny 6-ball WLCSP package
enable a small step-down dc-to-dc regulator solution.
The ADP2147 operates with an input voltage of 2.3 V to 5.5 V
and regulates an output voltage down to 0.8 V.
CONTROL SCHEME
The ADP2147 operates with a fixed frequency, current-mode
PWM control architecture at medium to high loads for high
efficiency but shifts to a power save mode control scheme at
light loads to lower the regulation power losses. When operating in
PWM mode, the duty cycle of the integrated switches is adjusted
and regulates the output voltage. When operating in power save
mode at light loads, the output voltage is controlled in a hyster-
etic manner, with higher V
OUT
ripple. During part of this time,
the converter is able to stop switching and enters an idle mode,
which improves conversion efficiency.
PWM MODE
In PWM mode, the ADP2147 operates at a fixed frequency of
3 MHz, set by an internal oscillator. At the start of each oscillator
cycle, the pFET switch is turned on, sending a positive voltage
across the inductor. Current in the inductor increases until the
magnitude of the current sense signal crosses the peak inductor
current threshold. This turns off the pFET switch and turns on the
nFET synchronous rectifier, which sends a negative voltage across
the inductor, causing the inductor current to decrease. The
synchronous rectifier stays on for the rest of the cycle.
The ADP2147 regulates the output voltage by adjusting the peak
inductor current threshold.
POWER SAVE MODE
The ADP2147 smoothly transitions to the power save mode of
operation when the load current decreases below the power
save mode current threshold. When the ADP2147 enters power
save mode, an offset is induced in the PWM regulation level,
which makes the output voltage rise. When the output voltage
reaches a level approximately 1.5% above the PWM regulation
level, PWM operation turns off. At this point, both power
switches are off, and the ADP2147 enters idle mode. C
OUT
discharges until V
OUT
falls to the PWM regulation voltage, at
which point the device drives the inductor to cause V
OUT
to rise
again to the upper threshold. This process is repeated for as long as
the load current is below the power save mode current
threshold.
Power Save Mode Current Threshold
The power save mode current threshold is set to 100 mA. The
ADP2147 employs a scheme that ensures that this current is
accurately controlled and independent of V
IN
and V
OUT
levels.
The control scheme also ensures that there is very little hysteresis
between the power save mode current threshold and that of the
PWM mode. The power save mode current threshold is opti-
mized for excellent efficiency across all load currents.
ENABLE/SHUTDOWN
The ADP2147 starts operating with soft start when the EN pin
is toggled from logic low to logic high. Pulling the EN pin low
forces the device into shutdown mode, reducing the supply
current to 0.2 A (typical).