Datasheet

ADP2126/ADP2127 Data Sheet
Rev. B | Page 4 of 20
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
TIMING See Figure 2 and Figure 3
VIN High to EXTCLK On
2
t
1
V
IN
= 2.1 V to 5.5 V 200 μs
EXTCLK On to V
OUT
Rising t
2 (CLOCK)
D
EXTCLK
= 40% to 60%, f
EXTCLK
= 6 MHz 250 320 400 μs
D
EXTCLK
= 40% to 60%, f
EXTCLK
= 27 MHz 250 320 400 μs
EXTCLK On to V
OUT
Rising t
2 (LOGIC)
EXTCLK = logic high 285 315 385 μs
V
OUT
Power-Up Time (Soft Start)
2
t
3
C
OUT
= 2.2 μF, R
LOAD
= 3.6 Ω 70 200 μs
EXTCLK Off to V
OUT
Falling t
5 (CLOCK)
D
EXTCLK
= 40% to 60%, f
EXTCLK
= 6 MHz to 27 MHz 9 17 μs
EXTCLK Off to V
OUT
Falling t
5 (LOGIC)
EXTCLK = logic high, no load 0 μs
V
OUT
Power-Down Time t
6
C
OUT
= 2.2 μF, R
LOAD
= 3.6 Ω 16 μs
C
OUT
= 2.2 μF, no load 465 μs
Minimum Shutdown Time
2
t
5
+ t
6
C
OUT
= 2.2 μF, no load 1400 μs
Minimum Power-Off Time
2
t
7
500 μs
1
The total shutdown current is the addition of VIN shutdown current and SW leakage.
2
Guaranteed by design.
3
Transients not included in voltage accuracy specifications.
4
The PFM output voltage will be higher than the PWM output voltage. See the Typi section. cal Performance Characteristics
5
Thermal shutdown protection is only active in PWM mode.
TIMING DIAGRAMS
t
6
t
7
t
5
t
3
t
2
t
1
V
OUT(NOM)
× 10%
V
IN
× 10%
V
IN
× 90%
VIN
V
OUT
EXTCLK
09658-003
Figure 2. Clock Enable I/O Timing Diagram
t
6
t
7
t
5
t
3
t
2
t
1
V
OUT(NOM)
× 10%
V
IN
× 10%
V
IN
× 90%
VIN
V
OUT
EXTCLK
09658-004
Figure 3. Logic Enable I/O Timing Diagram (Logic High Enable Feature Available Only on Certain Models)