Datasheet

Data Sheet ADP2126/ADP2127
Rev. B | Page 11 of 20
THEORY OF OPERATION
09658-029
SHOOT-
THROUGH
CONTROL
LOGIC
AND
PFM/PWM
CONTROL
THERMAL
SHUTDOWN
SOFT START
BANDGAP
BG
FB
BG
AGND
R1
FB
R2
V
OUT
AGND
AGND
FB
6MHz
OSCILLATOR
B2
THRESHOLD
DETECT*
THRESHOLD
DETECT
V
OUT
DISCHARGE
CLK
DETECT
SHORT-CIRCUIT
PROTECTION
COMPENSATION
EAMP
R
DSCHG
110Ω
RAMP
V(V
IN
)
ZXCOMP
PILIM
PDRIVE
PWM
COMP
PV
IN
C
IN
AVIN
NDRIVE
PREF
C
OUT
V
OUT
1.20V OR
1.26V
L
PGND
VIN
GND
SW
AGND
NREF
EXTCLK
C2
B1
A2
C1
A1
MODE
OFF
ON
ON
OFF
PWM
AUTO
OR
ADP2126/ADP2127
*
*
THE LOGIC HIGH ENABLE FEATURE IS ONLY AVAILABLE ON CERTAIN MODELS.
V
IN
2.1V TO 5.5V
Figure 28. Internal Block Diagram
OVERVIEW
The ADP2126/ADP2127 are high efficiency, synchronous, step-
down, dc-to-dc regulators that operate from a 2.1 V to 5.5 V
input voltage. They provide up to 500 mA of continuous output
current at a fixed output voltage. The 6 MHz operating frequency
enables the use of tiny external components. External control
for mode selection provides a power-saving option. The internal
control schemes of the ADP2126/ADP2127 give excellent
stability and transient response. Other internal features, such
as cycle-by-cycle peak current limit, soft start, undervoltage
lockout, output-to-ground short-circuit protection, and thermal
shutdown provide protection for internal circuit components.
EXTERNAL CLOCK (EXTCLK) ENABLE
The ADP2126/ADP2127 are enabled by a 6 MHz to 27 MHz
external clock signal applied to the EXTCLK pin. Certain models
can also be enabled with a logic high signal (see Figure 2, Figure 3,
and Figure 28). When the ADP2126/ ADP2127 are enabled, the
converter is able to power up, and the output voltage rises to its
nominal value. When the external clock is not switching and in
a low logic state, the ADP2126/ADP2127 stop regulating and
shut down to draw less than 0.3 µA (typical) from the source.