Datasheet

ADP2125
Rev. A | Page 11 of 16
t limit remains at
to operate.
ES
nt
power components during certain faults
e
et still
allows the converter to recover if the fault is removed.
voltage increases in stages to ensure that the converter is able to
start up effectively and in proper sequence. After the soft start
period expires, the peak PMOS switch curren
1 A (typical) and the part is able
PROTECTION FEATUR
Overcurrent Protection
To ensure that excessively high currents do not damage the
inductor, the ADP2125 incorporates cycle-by-cycle overcurre
protection. This function is accomplished by monitoring the
instantaneous peak current on the power PMOS switch. If this
current exceeds the PMOS switch current limit (1 A typical),
then the PMOS is immediately turned off. This minimizes the
potential for damage to
and transient events.
Output Short-Circuit Protection (SCP)
If the output voltage is shorted to GND, a standard dc-to-dc
controller delivers maximum power into that short. This may
result in a potentially catastrophic failure. To prevent this, th
ADP2125 senses when the output voltage is below the SCP
threshold (typically 0.55 V). At this point, the controller turns
off for approximately 450 µs and then automatically initiates a
soft start sequence. This cycle repeats until the short is removed
or the part is disabled. Figure 18 shows this operating behavior
of the ADP2125 during a short-circuit fault. The SCP dramati-
cally reduces the power delivered into the short circuit, y
Thermal Shutdown (TSD) Protection
The ADP2125 also includes TSD protection. If the die tempera-
ture exceeds 146°C (typical), the TSD protection activates and
turns off the power devices. They remain off until the die
temperature falls 13°C (typical), at which point the converter
restarts.
Undervoltage Lockout (UVLO)
If the input voltage is below the UVLO threshold, the ADP2125
automatically turns off the power switches and places the part
in a low power consumption mode. This prevents potentially
erratic operation at low input voltages. The UVLO levels have
approximately 100 mV of hysteresis to ensure glitch-free startup.
TIMING CONSTRAINTS
Shutdown Time
When the ADP2125 enters shutdown mode after the EXTCLK
signal is removed, the ADP2125 must remain in shutdown for a
minimum of 1400 µs, if no load is applied, before the EXTCLK
signal can be reapplied. This allows all internal nodes to
discharge to an off state.
Power-Off Time
When V
IN
drops, thereby triggering UVLO, the ADP2125 has a
minimum power-off time (t
7
) of 500 µs that must elapse before
V
IN
can be reapplied. This allows all supplies to discharge
enough power so that all internal devices are in an off state.
t
7
V
IN
× 10%
08774-021
Figure 21. Power-Off Time