Datasheet

Evaluation Board User Guide UG-199
Rev. 0 | Page 5 of 8
EVALUATION BOARD SCHEMATIC AND LAYOUT
VIN
GND
MODE
EN
FB
SW
VIN
CIN1
TP1
COUT
ADP2121
L1
B2
C1
A1
C2
A2
B1
CIN2
VOUT
TB1
MODE
JP2
(AUTO)
JP1
TB2
TB3
PGND
EN
(OFF)
VIN (PWM) VIN (ON)
U1
132
132
CIN3
09420-008
Figure 8. ADP2121 Evaluation Board Schematic
0
9420-009
Figure 9. PCB Top Layer
0
9420-010
Figure 10. PCB Bottom Layer
LAYOUT GUIDLINES
For high efficiency, good regulation, and stability with the
ADP2121, a well-designed PCB layout is essential. Use the
following guidelines when designing PCBs:
• Keep the low ESR input capacitor, CIN, close to VIN
and GND.
• Keep high current traces as short and as wide as possible.
• Avoid routing high impedance traces near any node
connected to SW or near the inductor to prevent radiated
noise injection.
• Keep the low ESR output capacitor, COUT, close to the FB
and GND pins of the ADP2121. Long trace lengths from
the part to the output capacitor add series inductance and
may cause instability or increased ripple.
APPLICATION NOTE
It is recommended that the VIN pin be bypassed with a 2.2 μF
or larger ceramic input capacitor if a supply line has a distributed
capacitance of at least 10 μF. If not, at least a 10 μF capacitor is
recommended on the input supply pin. The input capacitor can
be increased without any limit for improved input voltage
filtering.