Datasheet
ADP2118 Data Sheet
Rev. C | Page 6 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. THE EXPOSED PAD SHOULD BE SOLDERED TO
AN EXTERNAL GROUND PLANE UNDERNEATH
THE IC FOR THERMAL DISSIPATION.
12
11
10
1
3
4
PVIN
SW
SW
9
SW
SYNC/MODE
TRK
2
FREQ
FB
6
PGND
5
GND
7
PGND
8
PGND
16 PGOO
D
15
EN
14
VIN
13
PVIN
TOP
VIEW
ADP2118
08301-002
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 SYNC/MODE
Synchronization Input (SYNC). Connect this pin to an external clock between 600 kHz and 1.4 MHz to
synchronize the switching frequency to the external clock (see the Oscillator and Synchronization section for
details).
CCM/PFM Selection (MODE). When this pin is connected to VIN, PFM mode is disabled and the ADP2118 only
works in continuous conduction mode (CCM). When this pin is connected to ground, PFM mode is enabled
and becomes active at light loads.
2 FREQ Frequency Selection. Connect to GND to select 600 kHz and VIN for 1.2 MHz.
3 TRK
Tracking Input. To track a master voltage, drive TRK from a voltage divider from the master voltage. If the
tracking function is not used, connect TRK to VIN.
4 FB
Feedback Voltage Sense Input. Connect to a resistor divider from V
OUT
. For the fixed output version, connect
to V
OUT
directly.
5 GND Analog Ground. Connect to the ground plane.
6, 7, 8 PGND Power Ground. Connect to the ground plane and to the output return side of the output capacitor.
9, 10, 11 SW Switch Node Output. Connect to the output inductor.
12, 13 PVIN
Power Input Pin. Connect this pin to the input power source. Connect a bypass capacitor between this pin
and PGND.
14 VIN
Bias Voltage Input Pin. Connect a bypass capacitor between this pin and GND and a small (10 Ω) resistor
between this pin and PVIN.
15 EN
Precision Enable Pin. The external resistor divider can be used to set the turn-on threshold. To enable the part
automatically, connect the EN pin to VIN. This pin has a 1 MΩ pull-down resistor to GND.
16 PGOOD Power-Good Output (Open Drain). Connect to a resistor to any pull-up voltage <5.5 V.
17 (EPAD) Exposed Pad The exposed pad should be soldered to an external ground plane underneath the IC for thermal dissipation.