Datasheet

Data Sheet ADP2118
Rev. C | Page 15 of 24
OSCILLATOR AND SYNCHRONIZATION
The internal oscillator of ADP2118 can be set to 600 kHz or
1.2 MHz. Drive the FREQ pin low for 600 kHz; drive FREQ
pin high for 1.2 MHz.
To synchronize the ADP2118, drive an external clock at the
SYNC/MODE pin. The frequency of the external clock can be
in the range of 600 kHz to 1.4 MHz. During synchronization,
the regulator operates in CCM mode only.
If the FREQ pin is low, the switching frequency is in phase with
the external clock; if the FREQ pin is high, the switching
frequency is 180
o
out of phase with the external clock.
CURRENT LIMIT AND SHORT-CIRCUIT
PROTECTION
The ADP2118 has a peak current limit protection circuit to
prevent current runaway. The peak current is limited at 5.2 A.
When the inductor peak current reaches the current limit value,
the high-side MOSFET turns off and the low-side MOSFET
turns on until the next cycle while the overcurrent counter
increments. If the overcurrent counter count exceeds 10, the
part enters hiccup mode. The high-side FET and low-side FET
are both turned off. The part remains in this mode for 4096
clock cycles and then attempts to restart from soft start. If the
current limit fault has cleared, the part resumes normal
operation. Otherwise, it reenters hiccup mode again after
counting 10 current-limit violations.
OVERVOLTAGE PROTECTION (OVP)
The output voltage is continuously monitored by a comparator
through the FB pin, which is at 0.6 V (typical) under normal
operation. This comparator is set to activate when the FB
voltage exceeds 0.66 V (typical), thus indicating an output
overvoltage condition. If the voltage remains above this
threshold for 16 clock cycles, the high-side MOSFET turns off
and the low-side MOSFET turns on until the current through it
reaches the limit (−0.9 A for forced continuous mode and 0 A
for PFM mode). Thereafter, both the MOSFETs are held in the
off state until FB falls below 0.54 V (typical), and then the part
restarts. The behavior of PGOOD under this condition is
described in the Power Good section.
UNDERVOLTAGE LOCKOUT (UVLO)
Undervoltage lockout circuitry is integrated on the ADP2118. If
the input voltage drops below 2.1 V, the ADP2118 shuts down,
and both the power switch and the synchronous rectifier turn
off. When the voltage rises again above 2.2 V, the soft start period
is initiated, and the part is enabled.
THERMAL SHUTDOWN
In the event that the ADP2118 junction temperature rises above
140°C, the thermal shutdown circuit turns off the regulator.
Extreme junction temperatures can be the result of high current
operation, poor circuit board design, and/or high ambient
temperature. A 15°C hysteresis is included so that when thermal
shutdown occurs, the ADP2118 does not return to operation
until the on-chip temperature drops below 125°C. When
coming out of thermal shutdown, soft start is initiated.
POWER GOOD
PGOOD is an active high, open-drain output and requires a
resistor to pull it up to a voltage. A high indicates that the
voltage on the FB pin (and therefore the output voltage) is
within 10% of the desired value. A low on this pin indicates that
the voltage on the FB pin is not within 10% of the desired value.
There is a 16 cycle waiting period after FB is detected as being
out of bounds. If FB returns to within the ±10% range, it is
ignored by PGOOD circuitry.