Datasheet
ADP2118 Data Sheet
Rev. C | Page 14 of 24
THEORY OF OPERATION
The ADP2118 is a step-down, dc-to-dc regulator that uses fixed
frequency, peak current-mode architecture with an integrated
high-side switch and low-side synchronous rectifier. The high
switching frequency and tiny 16-lead, 4 mm × 4 mm LFCSP_WQ
package allow for a small step-down dc-to-dc regulator solu-
tion. The integrated high-side switch (P-channel MOSFET) and
synchronous rectifier (N-channel MOSFET) yield high efficiency
at medium-to-full loads, and light load efficiency is improved
by PFM mode.
The ADP2118 operates with an input voltage from 2.3 V to
5.5 V and regulates the output voltage down to 0.6 V. T h e
ADP2118 is also available with preset output voltage options
of 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, and 1.0 V.
CONTROL SCHEME
The ADP2118 uses the fixed frequency, peak current mode
PWM control architecture and operates in PWM mode for
medium-to-full loads but shifts to PFM mode (if enabled) at
light loads to maintain high efficiency. When operating in fixed
frequency PWM mode, the duty cycle of the integrated switches
is adjusted to regulate the output voltage. When operating in
PFM mode at light loads, the switching frequency is adjusted to
regulate the output voltage.
The ADP2118 operates in PWM mode when the load current is
greater than the pulse-skipping threshold current. At load
currents below this value, the regulator smoothly transitions to
the PFM mode of operation.
PWM MODE OPERATION
In PWM mode, the ADP2118 operates at a fixed frequency set
by the FREQ pin. At the start of each oscillator cycle, the P-
channel MOSFET switch is turned on, putting a positive voltage
across the inductor. Current in the inductor increases until the
current sense signal crosses the peak inductor current level, turns
off the P-channel MOSFET switch, and turns on the N-channel
MOSFET synchronous rectifier. This puts a negative voltage
across the inductor, causing the inductor current to decrease.
The synchronous rectifier stays on for the rest of the cycle or
until the inductor current reaches zero, which causes the zero-
crossing comparator to turn off the N-channel MOSFET as well.
The peak inductor current level is set by V
COMP
. The V
COMP
is the
output of a transconductance error amplifier that compares the
feedback voltage with an internal 0.6 V reference.
PFM MODE OPERATION
When PFM mode is enabled, the ADP2118 smoothly transi-
tions to the variable frequency PFM mode of operation when
the load current decreases below the pulse-skipping threshold
current, switching only as necessary to maintain the output
voltage within regulation. When the output voltage drops below
regulation, the ADP2118 enters PWM mode for a few oscillator
cycles to increase the output voltage back to regulation. During the
wait time between bursts, both power switches are off, and the
output capacitor supplies all the load current. Because the output
voltage dips and recovers occasionally, the output voltage ripple
in this mode is larger than the ripple in the PWM mode of
operation.
SLOPE COMPENSATION
Slope compensation stabilizes the internal current control loop
of the ADP2118 when operating close to and beyond 50% duty
cycle to prevent subharmonic oscillations. It is implemented by
summing an artificial voltage ramp to the current sense signal
during the on-time of the P-channel MOSFET switch. This
voltage ramp depends on the output voltage. When operating at
high output voltages, there is more slope compensation. The
slope compensation ramp value determines the minimum
inductor that can be used to prevent subharmonic oscillations.
ENABLE/SHUTDOWN
The EN pin is a precision analog input that enables the device
when the voltage exceeds 1.2 V (typical) and has 100 mV
hysteresis. When the enable voltage falls below 1.1 V (typical)
the part turns off. To force the ADP2118 to automatically start
when input power is applied, connect EN to VIN.
When the ADP2118 is shut down, the soft start capacitor is
discharged. This causes a new soft start cycle to begin when the
part is reenabled.
An internal pull-down resistor (1 MΩ) prevents an accidental
enable if EN is left floating.
INTEGRATED SOFT START
The ADP2118 has integrated soft start circuitry to limit the
output voltage rise time and reduce inrush current at startup.
The soft start time is fixed at 2048 clock cycles.
If the output voltage is precharged prior to turn-on, the
ADP2118 prevents a reverse inductor current (that would
discharge the output capacity) until the soft start voltage
exceeds the voltage on the FB pin.
TRACKING
The ADP2118 has a tracking input, TRK, that allows the output
voltage to track another voltage (master voltage). It is especially
useful in core and I/O voltage tracking for FPGAs, DSPs, and
ASICs.
The internal error amplifier includes three positive inputs: the
internal reference voltage, the soft start voltage, and the TRK
voltage. The error amplifier regulates the FB voltage to the
lowest of the three voltages. To track a master voltage, tie the
TRK pin to a resistor divider from the master voltage.
If the TRK function is not used, connect the TRK pin to VIN.