Datasheet

ADP2116 Data Sheet
Rev. A | Page 28 of 36
CONTROL LOOP COMPENSATION
The ADP2116 uses a peak current-mode control architecture
for excellent load and line transient response. The external
voltage loop is compensated by a transconductance amplifier
with a simple external RC network between the COMP1 or
COMP2 pin and GND, as shown in Figure 69.
g
m
V
FBx
0.6V
ADP2116
COMPx
R
COMP
C
COMP
C
C2
GND
08436-069
Figure 69. Compensation Components
The basic control loop block diagram is shown in Figure 70. The
blocks and components shown enclosed within the dashed line in
Figure 70 are embedded inside each channel of the ADP2116.
V
COMP
C
COMP
R
COMP
g
m
V
REF
= 0.6V
V
IN
PULSE-
WIDTH
MODULATOR
I
L
V
OUT
INDUCTOR
CURRENT
SENSE
ADP2116
0
8436-070
Figure 70. Basic Control Loop Block Diagram
The control loop can be broken down into the following three
sections:
 V
OUT
to V
COMP
 V
COMP
to I
L
 I
L
to V
OUT
Correspondingly, there are three transfer functions:
(s)Zg
V
V
(s)V
(s)V
COMP
m
OUT
REF
OUT
COMP
 (10)
CS
COMP
L
G
(s)V
(s)I

(11)
(s)Z
(s)I
(s)V
FILT
L
OUT
 (12)
where:
s is the angular frequency that can be written as s = 2πf.
g
m
is the transconductance of the error amplifier, 550 μS.
G
CS
is the current-sense gain, 4 A/V.
V
OUT
is the output voltage of the converter.
V
REF
is the internal reference voltage, 0.6 V.
Z
COMP
is the impedance of the RC compensation network.
Z
FILT
is the impedance of the output filter.
Z
COMP
(s) is the impedance of the RC compensation network that
forms a pole at origin and a zero as expressed in Equation 13.
COMP
COMPCOMP
COMP
Cs
CRs
(s)Z





1
(13)
Z
FILT
(s) is the impedance of the output filter and is expressed as
OUT
LOAD
LOAD
FILT
C
Rs
R
(s)Z


1
(14)
where
s is the angular frequency that can be written as s = 2πf.
The overall loop gain, H(s), is obtained by multiplying the three
transfer functions previously mentioned as follows:
H(s) = g
m
× G
CS
×
OUT
REF
V
V
× Z
COMP
(s) × Z
FILT
(s) (15)
When the switching frequency (f
SW
), output voltage (V
OUT
), output
inductor (L), and output capacitor (C
OUT
) values are selected,
the unity crossover frequency of approximately 1/12 the
switching frequency can be targeted.
At the crossover frequency, the gain of the open-loop transfer
function is unity. This yields Equation 16 for the compensation
network impedance at the crossover frequency.
REF
OUT
CS
m
OUT
CROSS
CROSSCOMP
V
V
Gg
Cf
fZ






π2
)( (16)
To ensure that there is sufficient phase margin at the crossover
frequency, set the compensator zero to 1/8 of the crossover
frequency, as indicated in Equation 17.
8π2
1
CROSS
COMPCOMP
ZERO
f
CR
f



(17)
Solving Equation 16 and Equation 17 yields the values for the
compensation resistor and the compensation capacitor, as shown
in Equation 18 and Equation 19.


















REF
OUTOUT
CS
m
CROSS
COMP
V
VC
Gg
f
R
)π2(
9.0
(18)
COMP
ZERO
COMP
Rf
C


π2
1
(19)
Capacitor C
C2
(as shown in Figure 69) forms a pole with the
compensation resistor, R
COMP
, in the feedback loop to ensure
that the loop gain continues to decrease, or roll off, well beyond
the unity-gain crossover frequency. The value of C
C2
, if used, is
typically set to 1/40 of the compensation capacitor, C
COMP
.