Datasheet

Data Sheet ADP2116
Rev. A | Page 25 of 36
OPERATION MODE CONFIGURATION
The dual-channel ADP2116 can be configured to one of four
modes of operation by connecting the OPCFG pin as detailed
in Table 7. The configuration sets the current limit for each
channel and enables or disables the transition to pulse skip
mode at light loads.
In the dual-phase configuration, the outputs of the two channels
are connected together and generate a single dc output voltage,
V
OUT
. For this single combined dual-phase output, only Mode 1
(see Table 7) can be used. In this mode, the error amplifiers of
both phases are used. The feedback pins (FB1 and FB2) are tied
together, the compensation pins (COMP1 and COMP2) are tied
together, the soft start pins (SS1 and SS2) are tied together, and
the enable pins (EN1 and EN2) are tied together.
In addition, if the power-good feature is used, PGOOD1 and
PGOOD2 should be tied together and then connected to VDD
using a single pull-up resistor.
When the ADP2116 is synchronized to an external clock, the
converters always operate in fixed-frequency CCM and do not
enter pulse skip mode at light loads. In this case, when configuring
the OPCFG pin, choose forced PWM mode.
Table 7. Current-Limit Operation Mode and Configuration
Maximum Output Current, Peak Current Limit,
Mode
R
OPCFG
± 5%
I
OUT1
(A)/I
OUT2
(A)
I
LIMIT1
(A)/I
LIMIT2
(A)
Power Savings at Light Load
1 0 Ω to VDD 3/3 4.5/4.5 Forced PWM
2 82 kΩ to GND 3/3 4.5/4.5 Pulse skip enabled
3 47 kΩ to GND 3/2 4.5/3.3 Forced PWM
4 27 kΩ to GND 3/2 4.5/3.3 Pulse skip enabled