Datasheet

Data Sheet ADP2116
Rev. A | Page 19 of 36
SIMPLIFIED BLOCK DIAGRAM
THERMAL
SHUTDOWN
OTSD
V
DD
UVLO
UVLO
GND
HICCUP
TIMER
GATE
CONTROL
LOGIC AND
MOSFET
DRIVERS
WITH
ANTI-SHOOT-
THROUGH
PROTECTION
SLOPE
COMPENSATION/
RAMP GENERATOR
V
OUT
SELECTOR
UVLO
OSC_CH1
PULSE SKIP
ENABLE
OTSD
SCFG
OPCFG
EN1
COMP1
FREQ
SYNC/CLKOUT
OSC
PHASE
SHIFT
CURRENT LIMIT/
CONFIGURATION
OSC_CH1
OSC_CH2
CLIM_CH1
CLIM_CH2
PULSE SKIP ENABLE
PGOOD1
V
FB1
0.7V
0.5V
SW1
VIN1
VIN2
VIN3
SW2
PGND1
PGND2
PMOS
NMOS
PWM
COMPARATOR
CURRENT-
LIMIT
COMPARATOR
CURRENT-SENSE
AMPLIFIER
CHANNEL 1
CLIM_CH1
V1SET
FB1
–
+
+
V
FB1
g
m
ERROR
AMPLIFIER
V
REF
= 0.6V
V
DD
I
SS
=
6µA
–
+
POWER
STAGE
SS1
HICCUP
TIMER
GATE
CONTROL
LOGIC AND
MOSFET
DRIVERS
WITH
ANTI-SHOOT-
THROUGH
PROTECTION
SLOPE
COMPENSATION/
RAMP GENERATOR
V
OUT
SELECTOR
UVLO
OSC_CH2
PULSE SKIP
ENABLE
OTSD
EN2
COMP2
PGOOD2
V
FB2
0.7V
0.5V
SW3
VIN4
VIN5
VIN6
SW4
PGND3
PGND4
PMOS
NMOS
PWM
COMPARATOR
CURRENT-
LIMIT
COMPARATOR
CURRENT-SENSE
AMPLIFIER
CHANNEL 2
CLIM_CH2
V2SET
FB2
–
+
+
V
FB2
g
m
ERROR
AMPLIFIER
V
REF
= 0.6V
V
DD
I
SS
=
6µA
–
+
POWER
STAGE
SS2
08436-057
Figure 57. Simplified Block Diagram