Datasheet

ADP2116 Data Sheet
Rev. A | Page 16 of 36
CH3 5.0V
CH2 1.0V
CH4 2.0A
M10.0µs 1.25GS/s A CH2 1.12V
2
3
4
08436-047
SW3, SW4
IT 200ps/pt
Ω
B
W
B
W
B
W
V
OUT2
INDUCTOR CURRENT
Figure 47. Current Limit Entry (Zoomed In),
Channel 2: V
OUT2
= 1.8 V, 2 A Configuration, f
SW
= 600 kHz
CH3 5.0V
CH2 1.0V
CH4 2.0A
M2.0ms 5.0MS/s A CH4 1.72A
2
3
4
08436-048
SW3, SW4
200ns/pt
Ω
B
W
B
W
B
W
V
OUT2
INDUCTOR CURRENT
Figure 48. Hiccup Mode, f
SW
= 600 kHz, 6.8 ms Hiccup Cycle
CH3 5.0V
CH2 1.0V
CH4 2.0A
M2.0ms 1.25GS/s A CH2 1.12V
2
3
4
08436-049
SW3, SW4
IT 40ns/pt
B
W
Ω
B
W
B
W
INDUCTOR CURRENT
V
OUT2
Figure 49. Exiting Hiccup Mode, Channel 2: V
OUT2
= 1.8 V, f
SW
= 600 kHz
CH3 5.0V
CH1 5.0V
CH4 5.0V
M1.0µs 1.25GS/s
IT 100ps/pt
A CH1 3.0V
4
3
1
08436-050
B
W
B
W
B
W
EXTERNAL SYNC
CHANNEL 2 SW
CHANNEL 1 SW
Figure 50. External Synchronization, f
SYNC
= 1.5 MHz, f
SW
= 750 kHz
CH3 5.0V
CH1 5.0V
CH4 5.0V
M1.0µs 1.25GS/s A CH4 3.0V
3
1
4
08436-051
IT 100psns/pt
B
W
B
W
B
W
INTERNAL CLKOUT
CHANNEL 2 SW
CHANNEL 1 SW
Figure 51. Internal Clock Output, f
SW
= 600 kHz, f
CLKOUT
= 1.2 MHz
CH3 2.0V
CH1 2.0V CH2 2.0V
CH4 2.0V
M1.0µs 1.25GS/s A CH1 2.0V
2
3
4
1
08436-052
CHANNEL 1 SW
CHANNEL 3 SW
CHANNEL 2 SW
CHANNEL 4 SW
IT 400ps/pt
B
W
B
W
B
W
B
W
Figure 52. 4-Channel Operation, Two ADP2116 Devices, One Device
Synchronizes the Other, 90° Phase-Shifted Switch Nodes