Datasheet

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Configurable, Dual 3 A/Single 6 A,

Synchronous, Step-Down DC-to-DC Regulator

Data Sheet

ADP2116

Rev. A

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FEATURES

Configurable 3 A/3 A or 3 A/2 A dual-output load

combinations or 6 A combined single-output load

High efficiency: up to 95%

Input voltage, V

: 2.75 V to 5.5 V

Selectable fixed output voltage of 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V,

or 3.3 V, or adjustable output voltage to 0.6 V minimum

±1.5% accurate reference voltage

Selectable switching frequency of 300 kHz, 600 kHz, 1.2 MHz,

or synchronized from 200 kHz to 2 MHz

Optimized gate slew rate for reduced EMI

External synchronization input or internal clock output

Dual-phase, 180° phase-shifted PWM channels

Current mode for fast transient response

Pulse skip mode with light loads or forced PWM operation

Input undervoltage lockout (UVLO)

Independent enable inputs and power-good outputs

Overcurrent and thermal overload protection

Programmable soft start

32-lead, 5 mm × 5 mm LFCSP package

Supported by ADIsimPower™ design tool

APPLICATIONS

Point-of-load regulation

Telecommunications and networking systems

Consumer electronics

Industrial and instrumentation

Medical

GENERAL DESCRIPTION

The ADP2116 is a versatile, synchronous, step-down switching

regulator that satisfies a wide range of customer point-of-load

requirements. The two PWM channels can be configured to deliver

independent outputs at 3 A and 3 A (or at 3 A and 2 A) or can be

configured as a single interleaved output capable of delivering 6 A.

The two PWM channels are 180° phase shifted to reduce input

ripple current and input capacitance.

The ADP2116 provides high efficiency and can operate at

switching frequencies of up to 2 MHz. At light loads, the ADP2116

can be set to operate in pulse skip mode for higher efficiency or

in forced PWM mode for noise sensitive applications.

The ADP2116 is designed with an optimized slew rate to reduce

EMI emissions, allowing the device to power sensitive, high perfor-

mance signal chain circuits. The switching frequency can be set

to 300 kHz, 600 kHz, or 1.2 MHz, or it can be synchronized to an

external clock that minimizes the system noise. The bidirectional

TYPICAL APPLICATION CIRCUIT

30kΩ

820pF

30kΩ

820pF

47µF

22µF

OUT1

= 2.5V, 3A

= 600kHz

3.3µH

100µF

22µF 22µF

1µF

47µF

OUT2

= 1.2V, 3A

2.2µH

= 5V

10Ω

100kΩ

VDD

OPCFG

GND

SCFG

FREQ

27kΩ

V1SET

4.7kΩ

VIN1

VIN2

VIN3

SW1

SW2

FB1

COMP1

SS1

EN1

COMP2

PGND4

PGND3

FB2

V2SET

SYNC/CLKOUT

SW4

SW3

VIN6

VIN5

VIN4

EN2

PGOOD2

ADP2116

PGOOD2

SYNC

PGOOD1

8.2kΩ

SS2

10nF

PGND1

PGND2

PGOOD1

08436-001

Figure 1.

100

10 100 1k 10k

EFFICIENCY (%)

LOAD CURRENT (mA)

= 3.3V; V

OUT

= 1.2V

= 5.0V; V

OUT

= 3.3V

= 5.0V; V

OUT

= 2.5V

= 600kHz

08436-002

Figure 2. Typical Efficiency vs. Load Current

synchronization pin is also configurable as a 90° out-of-phase

output clock, providing the possibility for a stackable

multiphase power solution.

The ADP2116 input voltage range is from 2.75 V to 5.5 V and can

convert to a fixed output of 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V

that can be set independently for each channel using external

resistors. If a resistor divider is used, the output voltage can be

set as low as 0.6 V. The ADP2116 operates over the −40°C to

+125°C junction temperature range.

Summary of content (36 pages)

PAGE 1
Configurable, Dual 3 A/Single 6 A, Synchronous, Step-Down DC-to-DC Regulator ADP2116 Data Sheet FEATURES TYPICAL APPLICATION CIRCUIT VIN = 5V 10Ω VIN6 PGOOD2 PGOOD2 VOUT2 = 1.2V, 3A 47µF 2.2µH SW3 EN1 VIN1 22µF VIN2 VIN3 PGOOD1 SW1 PGOOD1 3.3µH VOUT1 = 2.5V, 3A ADP2116 SW2 SW4 100µF 47µF PGND1 PGND3 22µF PGND2 PGND4 4.7kΩ 30kΩ 820pF FB1 FB2 V2SET V1SET SYNC/CLKOUT COMP1 SS1 10nF COMP2 SS2 SCFG GND SYNC 27kΩ 10nF 30kΩ 820pF 08436-001 8.2kΩ fSW = 600kHz Figure 1.
PAGE 2
ADP2116 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Overload Protection .................................................. 22 Applications ....................................................................................... 1 Maximum Duty Cycle Operation ............................................ 22 General Description .........................................................................
PAGE 3
Data Sheet ADP2116 SPECIFICATIONS If unspecified, VDD = VINx = EN1 = EN2 = 5.0 V. The minimum and maximum specifications are valid for TJ = −40°C to +125°C, unless otherwise specified. Typical values are at TJ = 25°C. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Table 1.
PAGE 4
ADP2116 Parameter SYNC Pin Capacitance to GND SYNC Input Logic Low SYNC Input Logic High Phase Shift Between Channels CLKOUT Frequency CLKOUT Positive Pulse Time CLKOUT Rise or Fall Time CURRENT LIMIT Data Sheet Symbol CSYNC VIL_SYNC VIH_SYNC Conditions fCLKOUT fCLKOUT = 2 × fSW FREQ tied to GND FREQ via 8.
PAGE 5
Data Sheet ADP2116 ABSOLUTE MAXIMUM RATINGS Table 2.
PAGE 6
ADP2116 Data Sheet 32 31 30 29 28 27 26 25 FB1 V1SET SS1 PGOOD1 EN1 VIN1 VIN2 VIN3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 ADP2116 TOP VIEW (Not to Scale) THERMAL PAD 24 23 22 21 20 19 18 17 SW1 SW2 PGND1 PGND2 PGND3 PGND4 SW3 SW4 NOTES 1. CONNECT THE EXPOSED THERMAL PAD TO THE SIGNAL/ANALOG GROUND PLANE. 08436-003 FB2 V2SET SS2 PGOOD2 EN2 VIN4 VIN5 VIN6 9 10 11 12 13 14 15 16 GND COMP1 FREQ SCFG SYNC/CLKOUT OPCFG COMP2 VDD Figure 3. Pin Configuration Table 3.
PAGE 7
Data Sheet Pin No. 14 15 16 17 Mnemonic VIN4 VIN5 VIN6 SW4 18 SW3 19 20 21 22 23 PGND4 PGND3 PGND2 PGND1 SW2 24 SW1 25 26 27 28 VIN3 VIN2 VIN1 EN1 29 PGOOD1 30 SS1 31 V1SET 32 FB1 EP ADP2116 Description Power Supply Input. The source of the high-side internal power MOSFET of Channel 2. Power Supply Input. The source of the high-side internal power MOSFET of Channel 2. Power Supply Input. The source of the high-side internal power MOSFET of Channel 2. Switch Node Output.
PAGE 8
ADP2116 Data Sheet 95 95 90 90 85 85 80 75 60 10 100 1k 10k 55 10 95 90 90 85 EFFICIENCY (%) 95 80 75 65 60 10 100 1k VIN = 3.3V 80 VIN = 5V 75 70 65 PULSE SKIP FORCED PWM PULSE SKIP FORCED PWM 60 10k LOAD CURRENT (mA) 08436-005 VOUT = 2.5V, VOUT = 2.5V, VOUT = 1.2V, VOUT = 1.2V, 10k Figure 6. Efficiency vs. Load, VOUT = 1.2 V and fSW = 1.2 MHz; Inductor TOKO FDV0620-1R0M, 1.0 µH, 14 mΩ 100 85 1k 100 LOAD CURRENT (mA) Figure 4. Efficiency vs.
PAGE 9
Data Sheet ADP2116 0.25 0.25 0.20 0.20 VOUT2 ERROR, NORMALIZED (%) 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 0.05 0 –0.05 –0.10 –0.15 1.0 1.5 2.0 2.5 3.0 LOAD CURRENT (A) –0.25 Figure 8. Load Regulation, Channel 1: VIN = 5 V, fSW = 600 kHz, and TA = 25°C 0 1.0 1.5 2.0 2.5 3.0 LOAD CURRENT (A) Figure 11. Load Regulation, Channel 2: VIN = 5 V, fSW = 600 kHz, and TA = 25°C 0.5 0.4 0.4 VOUT2 ERROR, NORMALIZED (%) 0.5 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 4.
PAGE 10
ADP2116 Data Sheet 250 320 200 310 175 fSW (kHz) MINIMUM ON TIME (ns) 225 330 fSW = 300kHz fSW = 600kHz fSW = 1.2MHz 150 300 125 290 100 280 3.0 3.5 4.0 4.5 5.0 5.5 VIN (V) 270 2.5 08436-014 50 2.5 3.5 4.0 4.5 5.0 5.5 VIN (V) Figure 14. Minimum On Time, Open Loop, Includes Dead Time Figure 17. Switching Frequency vs. Input Voltage, fSW = 300 kHz 350 660 330 fSW = 300kHz fSW = 600kHz fSW = 1.2MHz 640 310 290 620 270 fSW (kHz) MINIMUM OFF TIME (ns) 3.
PAGE 11
Data Sheet ADP2116 330 2.0 ENABLE/DISABLE THRESHOLD (V) 1.9 320 fSW (kHz) 310 VIN = 2.75V 300 VIN = 5.5V 290 280 1.8 1.7 1.6 1.5 ENABLE; VIN = 5.5V ENABLE; VIN = 2.75V DISABLE; VIN = 5.5V DISABLE; VIN = 2.75V 1.4 1.3 1.2 1.1 1.0 25 50 75 100 125 TEMPERATURE (°C) 0.8 –50 75 100 125 125 UVLO THRESHOLD (V) 2.7 620 VIN = 2.75V 600 VIN = 5.5V 580 VDD RISING 2.6 2.5 VDD FALLING 2.4 560 0 25 75 50 100 125 TEMPERATURE (°C) 2.
PAGE 12
ADP2116 Data Sheet 6.0 120 5.0 105 100 95 3A OPTION 4.5 110 CURRENT LIMIT (A) PGOOD1/PGOOD2 THRESHOLD (%) 5.5 115 OVERVOLTAGE, VOUT RISING OVERVOLTAGE, VOUT FALLING UNDERVOLTAGE, VOUT RISING UNDERVOLTAGE, VOUT FALLING 4.0 3.5 2A OPTION 3.0 2.5 2.0 1.5 90 1.0 85 25 50 75 100 125 TEMPERATURE (°C) 0 –50 25 50 75 100 125 125 Figure 29. Peak Current Limit vs. Temperature, VIN = 5 V 700 10 9 650 8 600 7 550 6 gm (µA/V) SHUTDOWN CURRENT (µA) 0 TEMPERATURE (°C) Figure 26.
PAGE 13
Data Sheet ADP2116 5.0 4.5 4.5 VDD SUPPLY CURRENT (mA) 5.0 4.0 3.5 3.0 FORCED PWM 2.0 PULSE SKIP 1.0 2.5 3.0 3.0 3.5 4.0 4.5 5.0 5.5 2.0 1.0 2.5 3.0 3.5 4.0 4.5 4.5 VDD SUPPLY CURRENT (mA) 5.0 4.0 3.5 3.0 FORCED PWM 2.0 3.5 3.0 2.5 2.0 VDD VDD VDD VDD 3.5 4.0 4.5 5.0 VDD VOLTAGE (V) 5.5 08436-032 1.5 3.0 5.5 4.0 PULSE SKIP 1.0 2.5 5.0 Figure 33. VDD Supply Current, No Load, Channel 1: VOUT1 = 1.5 V, Channel 2: VOUT2 = 0.8 V, fSW = 1.2 MHz 5.0 1.5 4.
PAGE 14
ADP2116 Data Sheet LOAD TRANSIENT RESPONSE VOUT2, AC VOUT1, AC 2 2 IOUT2 IOUT1 4 4 SW3, SW4 SW1, SW2 2.16A 08436-035 CH3 5.0V BW CH2 100mV BW M400µs 62.5MS/s A CH4 CH4 2.0A Ω BW 16ns/pt CH3 5V Figure 35. Load Transient Response in Pulse Skip Mode, Channel 1: 0.3 A to 3 A Load Step, VIN = 5 V, VOUT = 2.5 V, fSW = 600 kHz (See Table 12 for the Circuit Details) W CH2 50mV BW M200µs 125MS/s A CH4 CH4 2.0A Ω BW 8ns/pt 2.16A Figure 38. Load Transient Response in Pulse Skip Mode, Channel 2: 0.
PAGE 15
Data Sheet ADP2116 BASIC FUNCTIONALITY VOUT, AC 2 EN1 1 SW VOUT1 2 3 SS1 4 INDUCTOR CURRENT SW1, SW2 4 B W B CH2 10mV W M4µs 1.25GS/s A CH3 CH4 500mA Ω BW IT 400ps/pt 4.32V CH1 5.0V CH3 5.0V Figure 41. Pulse Skip Mode, 110 mA Load B W B W CH2 1.0V CH4 2.0V B M1.0ms 10MS/s 100ns/pt W B W A CH1 2.4V 08436-044 CH3 2.0V 08436-041 3 Figure 44. Soft Start, Channel 1: VOUT = 1.8 V, CSS1 = 10 nF VOUT, AC 2 EN1 1 VOUT1 SW 2 3 4 SS1 INDUCTOR CURRENT SW1, SW2 4 2.52V CH1 5.
PAGE 16
ADP2116 Data Sheet EXTERNAL SYNC INDUCTOR CURRENT 1 4 CHANNEL 1 SW VOUT2 2 4 CHANNEL 2 SW SW3, SW4 3 B W CH1 5.0V CH3 5.0V B W B W B CH4 5.0V W M1.0µs 1.25GS/s IT 100ps/pt A CH1 3.0V 08436-050 CH3 5.0V 1.12V 08436-047 3 CH2 1.0V BW M10.0µs 1.25GS/s A CH2 CH4 2.0A Ω BW IT 200ps/pt Figure 50. External Synchronization, fSYNC = 1.5 MHz, fSW = 750 kHz Figure 47. Current Limit Entry (Zoomed In), Channel 2: VOUT2 = 1.
PAGE 17
Data Sheet ADP2116 PHASE 1 SW EN1 1 1 PHASE 2 SW VOUT1 4 2 PGOOD1 3 INDUCTOR CURRENT, PHASE 1 2 3 SS1 INDUCTOR CURRENT, PHASE 2 B W CH2 1.0V CH4 1.0V B W B W M1ms 25MS/s 40ns/pt A CH1 2.2V CH1 5.0V CH2 2.0A Ω CH3 2.0A Ω CH4 5.0V 08436-053 CH1 5.0V CH3 5.0V Figure 53. Power-Good Signal M2.0µs T 79.6% A CH1 1.9V Figure 54. Combined Dual-Phase Output Operation, VOUT = 1.2 V, fSW = 300 kHz, 6 A Load Rev.
PAGE 18
ADP2116 Data Sheet BODE PLOTS 120 50 120 40 96 40 96 72 30 48 20 24 0 0 MAGNITUDE 10 48 24 MAGNITUDE 0 0 –10 –24 –10 –24 –20 –48 –20 –48 –30 –72 –30 –72 –40 –96 –40 –96 –50 1k –120 –50 1k 10k M1 100k M2 –120 10k FREQUENCY (Hz) M2 M2 – M1 56.62kHz 0.029dB 55.02° 220.20kHz –18.743dB –0.468° 163.58kHz –18.772dB –55.494° M1 100k M2 FREQUENCY (Hz) 08436-055 FREQUENCY MAGNITUDE PHASE M1 PHASE (Degrees) MAGNITUDE (dB) 10 72 PHASE Figure 55.
PAGE 19
Data Sheet ADP2116 SIMPLIFIED BLOCK DIAGRAM VDD GND UVLO SCFG FREQ OSC SYNC/CLKOUT UVLO OSC_CH1 PHASE SHIFT OSC_CH2 VFB1 CLIM_CH1 OPCFG PGOOD1 0.7V CURRENT LIMIT/ CONFIGURATION CLIM_CH2 VIN1 PULSE SKIP ENABLE 0.5V VIN2 VIN3 EN1 COMP1 UVLO V1SET VOUT SELECTOR FB1 OSC_CH1 VFB1 SS1 ISS = 6µA – + + PULSE SKIP ENABLE OTSD gm ERROR GATE CONTROL LOGIC AND MOSFET DRIVERS WITH ANTI-SHOOTTHROUGH PROTECTION PMOS NMOS PGND1 PGND2 AMPLIFIER VREF = 0.
PAGE 20
ADP2116 Data Sheet THEORY OF OPERATION The ADP2116 also includes undervoltage lockout (UVLO) with hysteresis, soft start, and power good, as well as protection features such as output short-circuit protection and thermal shutdown. The output voltages, current limits, switching frequency, pulse skip operation, and soft start time are externally programmable with tiny resistors and capacitors.
PAGE 21
Data Sheet ADP2116 The capacitance value of the soft start capacitor defines the soft start time, tSS, based on VREF I SS = t SS CSS (1) where: VREF is the internal reference voltage, 0.6 V. ISS is the soft start current, 6 µA. CSS is the soft start capacitor value.
PAGE 22
ADP2116 Data Sheet HICCUP MODE CURRENT LIMIT MAXIMUM DUTY CYCLE OPERATION The ADP2116 features a hiccup mode current-limit implementation. When the peak inductor current exceeds the preset current limit for more than eight consecutive clock cycles, the hiccup mode current-limit condition occurs. The channel then goes to sleep for 6.8 ms (at a 600 kHz switching frequency), which is enough time for the output to be discharged and the average power dissipation to be reduced. After the 6.
PAGE 23
Data Sheet ADP2116 CONVERTER CONFIGURATION To set the output voltage, VOUT1 or VOUT2, select one of the six fixed voltages, as shown in Table 4, by connecting the V1SET or V2SET pin to GND through a resistor of an appropriate value (see Figure 62). V1SET and V2SET set the voltage output levels for Channel 1 and Channel 2, respectively. The feedback pin, FB1 or FB2, should be directly connected to VOUT1 or VOUT2. Table 4. Output Voltage Programming 0 Ω to VDD VOUT1 (V) 0.8 1.2 1.5 1.8 2.5 3.3 0.6 to <1.
PAGE 24
ADP2116 Data Sheet SETTING THE OSCILLATOR FREQUENCY The ADP2116 channels can be set to operate in one of three preset switching frequencies: 300 kHz, 600 kHz, or 1.2 MHz. For 300 kHz operation, connect the FREQ pin to GND. For 600 kHz or 1.2 MHz operation, connect a resistor between the FREQ pin and GND (see Table 5). Table 5.
PAGE 25
Data Sheet ADP2116 OPERATION MODE CONFIGURATION The dual-channel ADP2116 can be configured to one of four modes of operation by connecting the OPCFG pin as detailed in Table 7. The configuration sets the current limit for each channel and enables or disables the transition to pulse skip mode at light loads. In the dual-phase configuration, the outputs of the two channels are connected together and generate a single dc output voltage, VOUT.
PAGE 26
ADP2116 Data Sheet EXTERNAL COMPONENTS SELECTION ADIsimPower DESIGN TOOL The ADP2116 is supported by ADIsimPower design tool set. ADIsimPower is a collection of tools that produce complete power designs optimized for a specific design goal. The tools enable the user to generate a full schematic, bill of materials, and calculate performance in minutes.
PAGE 27
Data Sheet ADP2116 To avoid saturation, the rated current of the inductor must be larger than the maximum peak inductor current, IL_PEAK, given by I L _ PEAK = I LOAD _ MAX + ∆I L 2 (6) where: ILOAD_MAX is the maximum dc load current. ΔIL is the peak-to-peak inductor ripple current. •  3 COUT_MIN ≅ ΔI OUT_STEP ×   f SW × ΔVDROOP • • • OUTPUT CAPACITOR SELECTION The output capacitor selection affects both the output voltage ripple and the loop dynamics of the converter.
PAGE 28
ADP2116 Data Sheet CONTROL LOOP COMPENSATION The ADP2116 uses a peak current-mode control architecture for excellent load and line transient response. The external voltage loop is compensated by a transconductance amplifier with a simple external RC network between the COMP1 or COMP2 pin and GND, as shown in Figure 69. ADP2116 ZCOMP(s) is the impedance of the RC compensation network that forms a pole at origin and a zero as expressed in Equation 13.
PAGE 29
Data Sheet ADP2116 DESIGN EXAMPLE the actual PCB footprint area of the converter will be larger because of the bigger inductor and output capacitors. The external component selection procedure from the Control Loop Compensation section is used for this design example. 3. Table 9. 2-Channel, Step-Down DC-to-DC Converter Requirements Parameter Input Voltage, VIN Output Voltage for Channel 1, VOUT1 Specification 5.0 V ±10% 2.5 V, 3 A, 1% VOUT p-p ripple Output Voltage for Channel 2, VOUT2 1.
PAGE 30
ADP2116 5. Data Sheet Calculate the compensation component values of the feedback loop by using the following equation:  (2π) f CROSS RCOMP = 0.9 ×   g m G CS   C OUT VOUT ×   V REF   However, the actual duty cycle will be larger than the calculated values to compensate for the power losses in the converter. Therefore, add 5% to 7% to the value calculated for the maximum load.     where: gm = 550 µS. GCS = 4 A/V. VREF = 0.6 V. VOUT = 2.5 V. COUT = 0.
PAGE 31
Data Sheet 5. ADP2116 Calculate the compensation component values of the feedback loop by using the following equation:  (2π) f CROSS RCOMP = 0.9 ×   g m G CS   C OUT VOUT ×   V REF   SYSTEM CONFIGURATION Complete the following steps to further configure the ADP2116 for this design example:     1. where: gm = 550 µS. GCS = 4 A/V. VREF = 0.6 V. VOUT = 1.2 V. COUT = 0.8 × (47 + 100) µF (capacitance derated by 20% to account for dc bias). From Equation 18, RCOMP = 30 kΩ.
PAGE 32
ADP2116 Data Sheet APPLICATION CIRCUITS VIN = 5V 10Ω 1µF 100kΩ 100kΩ PGOOD2 2.2µH VOUT2 = 1.2V, 3A 47µF VIN6 PGOOD2 VIN3 PGOOD1 VDD VIN5 VIN4 22µF SW3 22µF VIN2 ADP2116 SW4 100µF EN1 VIN1 OPCFG EN2 PGOOD1 3.3µH VOUT1 = 2.5V, 3A SW1 SW2 PGND1 PGND3 47µF 22µF PGND2 PGND4 4.7kΩ SYNC FB1 FB2 V2SET V1SET 10nF COMP1 SS1 SCFG GND 30kΩ COMP2 SS2 FREQ SYNC/CLKOUT 27kΩ 10nF 30kΩ 820pF 08436-071 8.2kΩ 820pF fSW = 600kHz Figure 71.
PAGE 33
Data Sheet ADP2116 VIN = 5V 10Ω 1µF 100kΩ 22µF VDD EN2 VIN4 EN1 VIN1 SCFG 100kΩ VIN3 PGOOD1 VIN6 PGOOD2 PGOOD2 VOUT2 = 3.3V, 2A 6.8µH SW3 PGOOD1 4.7µH SW1 ADP2116 SW4 VOUT1 = 1.8V, 3A SW2 PGND1 PGND3 100µF 22µF VIN2 VIN5 47µF 100µF PGND2 PGND4 47kΩ CLKOUT FB1 FB2 V2SET 15kΩ V1SET GND COMP1 SS1 22kΩ 10nF fSW = 300kHz 2.2nF 08436-073 1.6nF FREQ 10nF COMP2 SS2 27kΩ 30kΩ OPCFG SYNC/CLKOUT Figure 73. Application Circuit for 3 A/2 A Outputs VIN = 3.
PAGE 34
ADP2116 Data Sheet POWER DISSIPATION AND THERMAL CONSIDERATIONS Power dissipated by the ADP2116 dual switching regulator is a major factor that affects the efficiency of the two dc-to-dc converters. The efficiency is given by Efficiency  POUT  100% PIN PLOSS = PIN − POUT (22) (27) The proportionality coefficient is defined as the thermal resistance from the junction of the die to the ambient temperature.
PAGE 35
Data Sheet ADP2116 CIRCUIT BOARD LAYOUT RECOMMENDATIONS • • • • • • Use separate analog and power ground planes. Connect the ground reference of sensitive analog circuitry, such as output voltage divider components, to analog ground. In addition, connect the ground references of power components, such as input and output capacitors, to power ground. Connect both ground planes to the exposed pad of the ADP2116.
PAGE 36
ADP2116 Data Sheet OUTLINE DIMENSIONS 5.00 BSC SQ 0.60 MAX 0.60 MAX 25 32 1 24 0.50 BSC 3.25 3.10 SQ 2.95 EXPOSED PAD 17 TOP VIEW 1.00 0.85 0.80 0.80 MAX 0.65 TYP 12° MAX 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.30 0.25 0.18 SEATING PLANE 0.50 0.40 0.30 8 16 9 BOTTOM VIEW 0.25 MIN 3.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 05-23-2012-A 4.