Datasheet

ADP2114 Data Sheet
Rev. B | Page 36 of 40
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Good circuit board layout is essential in obtaining the best
performance from each channel of the ADP2114. Poor circuit
layout degrades the output ripple and regulation, as well as the
EMI and electromagnetic compatibility performance. For
optimum layout, refer to the following guidelines:
• Use separate analog and power ground planes. Connect the
ground reference of sensitive analog circuitry, such as output
voltage divider components, to analog ground. In addition,
connect the ground references of power components, such as
input and output capacitors, to power ground. Connect
both ground planes to the exposed pad of the ADP2114.
• Place the input capacitor of each channel as close to the
VINx pins as possible and connect the other end to the
closest power ground plane.
• For low noise and better transient performance, a filter is
recommended between VINx and VDD. Place a 1 µF, 10 Ω
low-pass input filter between the VDD pin and the VINx
pins, as close to the GND pin as possible.
• Ensure that the high current loop traces are as short and as
wide as possible. Make the high current path from C
IN
through L, C
OUT
, and the power ground plane back to C
IN
as
short as possible. To accomplish this, ensure that the input and
output capacitors share a common power ground plane. In
addition, make the high current path from the PGNDx pin
through L and C
OUT
back to the power ground plane as
short as possible. To do this, ensure that the PGNDx pin of
the ADP2114 is tied to the PGND plane as close as possible
to the input and output capacitors (see Figure 84).
• Connect the ADP2114 exposed pad to a large copper plane
to maximize its power dissipation capability. Thermal
conductivity can be obtained using the method described
in JEDEC specification JESD51-7.
• Place the feedback resistor divider network as close as
possible to the FBx pin to prevent noise pickup. Try to
minimize the length of the trace connecting the top of the
feedback resistor divider to the output while keeping away
from the high current traces and the switch node, SWx, that
can lead to noise pickup. To reduce noise pickup, place an
analog ground plane on either side of the FBx trace and
make it as small as possible to reduce the parasitic
capacitance pickup.
08143-084
1µF
GND VDD
ADP2114
VINx
SWx
PGNDx
L
FBx
GND
LOAD
10Ω
V
IN
C
IN
C
OUT
V
OUT
Figure 84. High Current Traces in the PCB Circuit