Datasheet

Data Sheet ADP2114
Rev. B | Page 35 of 40
POWER DISSIPATION, THERMAL CONSIDERATIONS
Power dissipated by the ADP2114 dual switching regulator is a
major factor that affects the efficiency of the two dc-to-dc
converters. The efficiency is given by
100%
IN
OUT
P
P
Efficiency (21)
where:
P
IN
is the input power.
P
OUT
is the output power.
Power loss is given by P
LOSS
= P
IN
− P
OUT
.
The power loss of the step-down dc-to-dc converter is
approximated by
P
LOSS
= P
D
+ P
L
(22)
where:
P
D
is the power dissipation on the ADP2114.
P
L
is the inductor power losses.
The inductor losses are estimated (without core losses) by
P
L
 I
OUT
2
× DCR
L
(23)
where:
I
OUT
is the dc load current.
DCR
L
is the inductor series resistance.
The ADP2114 power dissipation, P
D
, includes the power switch
conductive losses, the switch losses, and the transition losses of
each channel.
The power switch conductive losses are due to the output current,
I
OUT
, flowing through the PMOSFET and the NMOSET power
switches that have internal resistance, R
DSON
. The amount of
conductive power loss is found by
P
COND
= [R
DSON-P
× D + R
DSON-N
× (1 − D)] × I
OUT
2
(24)
where the duty-cycle, D, = V
OUT
/V
IN
.
Switching losses are associated with the current drawn by the
driver to turn on and turn off the power devices at the switching
frequency. The amount of switching power loss is given by
P
SW
= (C
GATE-P
+ C
GATE-N
) × V
IN
2
× f
SW
(25)
where:
C
GATE-P
is the PMOSFET gate capacitance.
C
GATE-N
is the NMOSFET gate capacitance.
Transition losses occur because the P-channel power MOSFET
cannot be turned on or off instantaneously. The amount of
transition loss is calculated by
P
TRAN
= V
IN
× I
OUT
× (t
RISE
+ t
FALL
) × f
SW
(26)
where t
RISE
and t
FALL
are the rise time and the fall time of the
switching node, SW. In the ADP2114, the rise and fall times of
the switching node are in the order of 5 ns.
The power dissipated by the regulator increases the die junction
temperature, T
J
, above the ambient temperature, T
A
.
T
J
= T
A
+ T
R
(27)
where the temperature rise, T
R
, is proportional to the power
dissipation in the package, P
D
.
The proportionality coefficient is defined as the thermal resistance
from the junction of the die to the ambient temperature.
T
R
= θ
JA
× P
D
(28)
where
θ
JA
is the junction-ambient thermal resistance (34°C/W
for the JEDEC 1S2P board, see Table 2).
When designing an application for a particular ambient
temperature range, calculate the expected ADP2114 power
dissipation (P
D
) due to conductive, switching, and transition
losses of both channels by using Equation 24, Equation 25,
and Equation 26 and estimate the temperature rise by using
Equation 27 and Equation 28. The reliable operation of the
two converters can be achieved only if the estimated die junction
temperature of the ADP2114 (Equation 27) is less than 125°C.
Therefore, at higher ambient temperatures, reduce the power
dissipation of the system. Figure 83 provides the power derating
for the elevated ambient temperature at different air flow
conditions. The area below the curves is the safe operation area
for ADP2114 dual regulators.
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
70 11510085
MAXIMUM POWER DISSIPATION (W)
AMBIENT TEMPERATURE (°C)
08143-083
AIR VELOCITY = 0 LFM
AIR VELOCITY = 200 LFM
AIR VELOCITY = 500 LFM
Figure 83. Power Dissipation Derating (JEDEC 1S2P Board)