Datasheet

ManualsBrandsANALOG DEVICES ManualsPMICsPMIC - DC/DC voltage regulator Holder LFCSP-32-VQ

Configurable, Dual 2 A/Single 4 A,

Synchronous Step-Down DC-to-DC Regulator

Data Sheet

ADP2114

Rev. B Document Feedback

Information furnished

by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

FEATURES

Configurable 2 A/2 A or 3 A/1 A dual output load

combinations or 4 A combined single output

High efficiency: up to 95%

Input voltage V

: 2.75 V to 5.5 V

Selectable fixed output: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V or

adjustable output voltage to 0.6 V minimum

±1.5% accurate reference voltage

Selectable switching frequency: 300 kHz, 600 kHz, 1.2 MHz

or synchronized from 200 kHz to 2 MHz

Optimized gate slew rate for reduced EMI

External synchronization input or internal clock output

Dual-phase, 180° phase shifted PWM channels

Current mode for fast transient response

Pulse skip under light load or forced PWM operation

Input undervoltage lockout (UVLO)

Independent enable inputs and PGOOD outputs

Overcurrent and thermal overload protection

Externally programmable soft start

32-lead 5 mm × 5 mm LFCSP package

Supported by ADIsimPower™ design tool

APPLICATIONS

Point of load regulation

Telecommunications and networking systems

Consumer electronics

Industrial and Instrumentation

Medical

GENERAL DESCRIPTION

The ADP2114 is a versatile, synchronous step-down, switching

regulator that satisfies a wide range of customer point-of-load

requirements. The two PWM channels can be configured to

deliver independent outputs at 2 A and 2 A (or 3 A/1 A) or can be

configured as a single interleaved output capable of delivering 4 A.

The two PWM channels are 180º phase shifted to reduce input

ripple current and to reduce input capacitance. The ADP2114

provides high efficiency and operates at switching frequencies of

up to 2 MHz. At light loads, the ADP2114 can be set to operate

in pulse skip mode for higher efficiency or in forced PWM mode

to reduce EMI.

The ADP2114 is designed with an optimized gate slew rate to reduce

EMI emissions, allowing it to power sensitive, high performance

signal chain circuits. The switching frequency can be set to 300 kHz,

600 kHz, or 1.2 MHz and can be synchronized to an external clock

that minimizes the system noise. The bidirectional synchronization

pin is also configurable as a 90° out-of-phase output clock, providing

the possibility for a stackable multiphase power solution.

TYPICAL APPLICATION CIRCUIT

08143-001

22kΩ

1.2nF

22kΩ

1.2nF

47µF

OUT1

= 3.3V, 2A

= 600kHz

4.7µH

47µF

22µF 22µF

1µF

22µF

OUT2

= 1.8V, 2A

2.2µH

= 5V

10Ω

100kΩ100kΩ

VDD

GND

SCFG

OPCFG

FREQ

47kΩ

V1SET

15kΩ

VIN1

VIN2

VIN3

SW1

SW2

FB1

COMP1

SS1

EN1

COMP2

PGND4

PGND3

FB2

V2SET

SYNC/CLKOUT

SW4

SW3

VIN6

VIN5

VIN4

EN2

PGOOD2

ADP2114

PGOOD2

SYNC

PGOOD1

8.2kΩ

SS2

10nF

PGND1

PGND2

PGOOD1

Figure 1.

The ADP2114 input voltage range is from 2.75 V to 5.5 V, a n d it

converts to fixed outputs of 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, or

3.3 V that can be set independently for each channel using

external resistors. Using a resistor divider, it is also possible to

set the output voltage as low as 0.6 V. The ADP2114 operates

over the −40°C to +125°C junction temperature range.

100

0.01 0.1 1 3

EFFICIENCY (%)

LOAD CURRENT (A)

= 5.0V; V

OUT

= 3.3V

= 5.0V; V

OUT

= 1.8V

= 3.3V; V

OUT

= 1.8V

08143-002

Figure 2. Typical Efficiency vs. Load Current

Summary of content (40 pages)

PAGE 1
Configurable, Dual 2 A/Single 4 A, Synchronous Step-Down DC-to-DC Regulator ADP2114 Data Sheet FEATURES TYPICAL APPLICATION CIRCUIT APPLICATIONS Point of load regulation Telecommunications and networking systems Consumer electronics Industrial and Instrumentation Medical VIN = 5V 10Ω 100kΩ EN2 VIN4 EN1 VIN1 VDD 22µF VIN6 PGOOD2 PGOOD2 VOUT2 = 1.8V, 2A 2.2µH SW3 VIN3 PGOOD1 ADP2114 SW4 22µF SW1 PGOOD1 4.7µH VOUT1 = 3.
PAGE 2
ADP2114 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Overload Protection .................................................. 23 Applications ....................................................................................... 1 Maximum Duty Cycle Operation ............................................ 23 General Description .........................................................................
PAGE 3
Data Sheet ADP2114 SPECIFICATIONS If unspecified, VDD = VINx = EN1 = EN2 = 5.0 V. The minimum and maximum specifications are valid for TJ = −40°C to +125°C, unless otherwise specified. Typical values are at TJ = 25°C. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Table 1.
PAGE 4
ADP2114 Parameter SYNC Pin Capacitance to GND SYNC Input Logic Low SYNC Input Logic High Phase Shift Between Channels CLKOUT Frequency CLKOUT Positive Pulse Time CLKOUT Rise or Fall Time CURRENT LIMIT Data Sheet Symbol CSYNC VIL_SYNC VIH_SYNC Conditions fCLKOUT fCLKOUT = 2 × fSW FREQ tied to GND FREQ via 8.
PAGE 5
Data Sheet ADP2114 ABSOLUTE MAXIMUM RATINGS Table 2.
PAGE 6
ADP2114 Data Sheet 32 31 30 29 28 27 26 25 FB1 V1SET SS1 PGOOD1 EN1 VIN1 VIN2 VIN3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 ADP2114 TOP VIEW (Not to Scale) THERMAL PAD 24 23 22 21 20 19 18 17 SW1 SW2 PGND1 PGND2 PGND3 PGND4 SW3 SW4 NOTES 1. CONNECT THE EXPOSED THERMAL PAD TO THE SIGNAL/ANALOG GROUND PLANE. 08143-003 FB2 V2SET SS2 PGOOD2 EN2 VIN4 VIN5 VIN6 9 10 11 12 13 14 15 16 GND COMP1 FREQ SCFG SYNC/CLKOUT OPCFG COMP2 VDD Figure 3. Pin Configuration Table 3.
PAGE 7
Data Sheet Pin No. 14 15 16 17 Mnemonic VIN4 VIN5 VIN6 SW4 18 SW3 19 20 21 22 23 PGND4 PGND3 PGND2 PGND1 SW2 24 SW1 25 26 27 28 VIN3 VIN2 VIN1 EN1 29 PGOOD1 30 SS1 31 V1SET 32 FB1 EPAD (EP) ADP2114 Description Power Supply Input. The source of the high-side internal power MOSFET of Channel 2. Power Supply Input. The source of the high-side internal power MOSFET of Channel 2. Power Supply Input. The source of the high-side internal power MOSFET of Channel 2. Switch Node Output.
PAGE 8
ADP2114 Data Sheet 100 95 95 90 90 85 80 75 70 60 10 100 1k 80 VIN = 5V, VOUT = 2.5V FORCED PWM VIN = 5V, VOUT = 2.5V PULSE SKIP VIN = 3.3V, VOUT = 1.2V FORCED PWM VIN = 3.3V, VOUT = 1.2V PULSE SKIP 75 70 VOUT = 3.3V VOUT = 3.3V; PULSE SKIP VOUT = 1.8V VOUT = 1.8V; PULSE SKIP 65 85 65 10k LOAD CURRENT (mA) 60 10 100 1k 10k LOAD CURRENT (mA) Figure 4. Channel 1 Efficiency vs. Load, VIN = 5 V and fsw = 300 kHz; VOUT = 3.3 V, Inductor Cooper Bussmann DR1050-8R2-R, 8.
PAGE 9
Data Sheet ADP2114 0.50 –0.50 0 500 1000 1500 2000 2500 3000 LOAD CURRENT (mA) 0 0.4 VOUT ERROR, NORMALIZED (%) 0.5 0.2 0.1 0 –0.1 –0.2 –0.3 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.4 –0.5 2.5 –0.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Figure 9. Line Regulation, Channel 1: Load Current = 3 A and fSW = 600 kHz 0.75 0.50 0.50 VOUT ERROR (%) 0.75 0 –0.25 VIN = 2.75V; 3A LOAD 75 100 TEMPERATURE (°C) 125 08143-010 50 5.5 Figure 10. Output Voltage vs. Temperature, Channel 1: VOUT = 0.
PAGE 10
ADP2114 250 225 Data Sheet 330 fSW = 300kHz fSW = 600kHz 320 200 310 175 fSW (kHz) MINIMUM ON-TIME (ns) fSW = 1.2MHz 150 300 125 290 100 280 3.0 3.5 4.0 4.5 5.0 5.5 VIN (V) 270 2.5 08143-014 50 2.5 fSW = 1.2MHz 4.5 5.0 5.5 660 640 290 620 270 fSW (kHz) MINIMUM OFF-TIME (ns) fSW = 600kHz 310 4.0 Figure 17. Switching Frequency vs. Input Voltage, fSW = 300 kHz fSW = 300kHz 330 3.5 VIN (V) Figure 14. Minimum On-Time, Open Loop, Includes Dead Time 350 3.
PAGE 11
Data Sheet ADP2114 330 2.0 ENABLE/DISABLE THRESHOLD (V) 1.9 320 fSW (kHz) 310 VIN = 2.75V 300 VIN = 5.5V 290 280 1.8 1.7 1.6 ENABLE; VIN = 5.5V 1.5 ENABLE; VIN = 2.75V 1.4 DISABLE; VIN = 5.5V 1.3 DISABLE; VIN = 2.75V 1.2 1.1 1.0 25 0 75 50 100 125 TEMPERATURE (°C) 0.8 –50 08143-020 –25 25 50 75 100 125 Figure 23. Enable/Disable Threshold vs. Temperature 660 2.8 640 UVLO THRESHOLD (V) 2.7 620 VIN = 2.75V 600 VIN = 5.5V 580 VDD RISING 2.6 2.5 VDD FALLING 2.
PAGE 12
ADP2114 Data Sheet 6.0 120 OVERVOLTAGE; VOUT RISING 5.5 115 5.0 4.5 OVERVOLTAGE; VOUT FALLING CURRENT LIMIT (A) PGOOD THRESHOLD (%) 3A OPTION 110 105 100 95 UNDERVOLTAGE; VOUT RISING 4.0 2A OPTION 3.5 3.0 2.5 1A OPTION 2.0 1.5 90 UNDERVOLTAGE, VOUT FALLING 1.0 85 0 25 50 75 100 125 TEMPERATURE (°C) 0 –50 08143-026 –25 –25 0 25 50 75 100 125 TEMPERATURE (°C) Figure 26. PGOOD Threshold vs. Temperature 08143-029 0.5 80 –50 Figure 29. Peak Current Limit vs.
PAGE 13
Data Sheet ADP2114 SUPPLY CURRENT 5.0 5.0 4.5 4.5 4.0 4.0 VDD CURRENT (mA) VDD CURRENT (mA) FORCED PWM 3.5 3.0 2.5 FORCED PWM 2.0 3.5 3.0 2.5 PULSE SKIP 2.0 PULSE SKIP 1.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD VOLTAGE (V) 1.0 2.5 08143-031 1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD VOLTAGE (V) Figure 31. VDD Supply Current, No Load, Channel 1: VOUT = 1.5 V, Channel 2 Off, fSW = 1.2 MHz 08143-033 1.5 Figure 33. VDD Supply Current, No Load, Channel 1: VOUT = 1.5 V, Channel 2: VOUT = 0.
PAGE 14
ADP2114 Data Sheet LOAD TRANSIENT RESPONSE VOUT VOUT 2 2 IOUT IOUT 4 4 SW SW CH2 50mV CH4 2.0A M200µs 50MS/s 200ns/pt A CH2 –33mV 08143-035 CH1 5.0V CH3 5.0V Figure 35. Channel 1: VIN = 5 V, VOUT = 3.3V, fSW = 600 kHz; Forced PWM (See Table 12 for the Circuit Details) CH2 50mV CH4 1.0A M200µs 50MS/s 20ns/pt A CH2 –34mV 08143-038 3 1 Figure 38. Channel 2: VIN = 5 V, VOUT = 1.
PAGE 15
Data Sheet ADP2114 2 VOUT VOUT 2 VIN VIN SW CH1 5.0V CH3 1.0V CH2 10mV M400µs A CH3 4.86V 1 3 08143-041 1 3 CH1 5.0V CH3 1.0V Figure 41. 3.3 V to 5 V Line Transient, VOUT = 1.5 V, Load = 1 A fSW = 1.2 MHz, Pulse Skip Enabled CH2 10mV M400µs A CH3 3.50V 08143-044 SW Figure 44. 5 V to 3.3 V Line Transient, VOUT = 1.5 V, Load = 1 A fSW = 1.2 MHz, Forced PWM 2 VOUT VOUT 2 VIN VIN SW SW CH2 10mV M400µs A CH3 3.58V 3 08143-042 CH1 5.0V CH3 1.0V CH1 2.0V CH3 1.0V Figure 42.
PAGE 16
ADP2114 Data Sheet VOUT, AC 2 VOUT 2 SW VIN 3 SW INDUCTOR CURRENT 1 CH1 2.0V CH3 1.0V CH2 10mV M400µs A CH3 4.84V Figure 47. 3.3 V to 5 V Line Transient, VOUT = 0.6 V, Load = 1 A fSW = 600 kHz, Forced PWM CH3 2.0V CH2 20mV CH2 500mA M1µs A CH3 2.52V 08143-050 3 08143-047 4 Figure 50. Forced PWM Mode, CCM Operation, 200 mA Load, fSW = 600 kHz VOUT, AC VOUT 2 2 SW VIN SW 3 INDUCTOR CURRENT 1 CH2 10mV M400µs A CH3 3.50V Figure 48. 5 V to 3.3 V Line Transient, VOUT = 0.
PAGE 17
Data Sheet ADP2114 INDUCTOR CURRENT EN2 1 VOUT2 4 2 4 SS2 VOUT 2 SW SW 3 CH2 1.0V CH4 500mV M200µs A CH1 2.4V CH3 5.0V Figure 53. Start with Precharged Output CH2 1.0V CH4 2.0A M2.0ms A CH4 1.72V 08143-056 CH1 5.0V CH3 5.0V 08143-053 3 Figure 56. Hiccup Mode, fSW = 600 kHz, 6.8 ms Hiccup Cycle INDUCTOR CURRENT INDUCTOR CURRENT 4 4 VOUT2 VOUT 2 2 SW SW M1.0ms A CH2 1.12V CH3 5.0V Figure 54. Current Limit Entry, Channel 2 VOUT = 1.
PAGE 18
ADP2114 Data Sheet CHANNEL 1 SW EN2 1 4 VOUT2 2 CHANNEL 2 SW 3 PGOOD2 INTERNAL CLKOUT 4 SW 1 A CH3 3.0V CH1 5.0V CH3 5.0V Figure 59. Internal Clock Out, fSW = 600 kHz, fCLKOUT = 1.2 MHz CH2 1.0V CH4 2.0V M200µs A CH1 3.5V 08143-061 M1.0µs CH4 5.0V 1.9V 08143-062 CH1 5.0V CH3 5.0V 08143-059 3 Figure 61. Power Good Signal CHANNEL 1 SW INDUCTOR CURRENT, PHASE 2 CHANNEL 3 SW 1 4 2 INDUCTOR CURRENT, PHASE 1 2 PHASE 2 SW 3 CHANNEL 2 SW 3 4 CHANNEL 4 SW CH2 2.0V CH4 2.0V M1.
PAGE 19
Data Sheet ADP2114 BODE PLOTS 50 150 40 120 90 MAGNITUDE (dB) 20 PHASE 60 30 10 0 0 MAGNITUDE –10 –30 –20 –60 –30 –90 –40 –120 PHASE (Degrees) 30 –150 –50 1k M1 10k 100k M2 FREQUENCY MAGNITUDE PHASE M2 M2 – M1 54.86kHz 0.042dB 50.099° 210.34kHz –19.632dB –0.412° 155.48kHz –19.673dB –50.511° 08143-063 FREQUENCY (Hz) M1 Figure 63. VIN = 5 V, VOUT = 3.
PAGE 20
ADP2114 Data Sheet SIMPLIFIED BLOCK DIAGRAM VDD GND UVLO SCFG FREQ OSC SYNC/CLKOUT UVLO OSC_CH1 PHASE SHIFT OSC_CH2 VFB1 CLIM_CH1 OPCFG PGOOD1 0.7V CURRENT LIMIT/ CONFIGURATION CLIM_CH2 VIN1 PULSE SKIP ENABLE 0.5V VIN2 VIN3 EN1 GATE CONTROL LOGIC AND MOSFET DRIVERS WITH ANTI-SHOOT THROUGH PROTECTION COMP1 UVLO V1SET VOUT SELECTOR FB1 OSC_CH1 VFB1 SS1 ISS = 6µA – + + PULSE SKIP ENABLE OTSD gm ERROR PMOS NMOS PGND1 PGND2 AMPLIFIER VREF = 0.
PAGE 21
Data Sheet ADP2114 THEORY OF OPERATION ADIsimPower DESIGN TOOL The ADP2114 is supported by ADIsimPower design tool set. ADIsimPower is a collection of tools that produce complete power designs optimized for a specific design goal. The tools enable the user to generate a full schematic, bill of materials, and calculate performance in minutes.
PAGE 22
ADP2114 Data Sheet The power good circuitry monitors the output voltage on the FB1 (FB2) pin and compares it to the rising and falling thresholds shown in Table 1. If the output voltage, VOUT1 (VOUT2), exceeds the typical rising limit of 116% of the target output voltage, VOUT1SET (VOUT2SET), the PGOOD1 (PGOOD2) pin pulls low. The PGOOD1 (PGOOD2) pin continues to pull low until the output voltage recovers down to 108% (typical) of the target value.
PAGE 23
Data Sheet ADP2114 HICCUP MODE CURRENT LIMIT MAXIMUM DUTY CYCLE OPERATION The ADP2114 features a hiccup mode current limit implementation. When the peak inductor current exceeds the preset current limit for more than eight consecutive clock cycles, the hiccup mode current limit condition occurs. The channel then goes to sleep for 6.8 ms (at a 600 kHz switching frequency), which is enough time for the output to discharge and the average power dissipation to reduce.
PAGE 24
ADP2114 Data Sheet CONVERTER CONFIGURATION RV2SET (Ω) ± 5% 0 to GND 4.7 k to GND 8.2 k to GND 15 k to GND 27 k to GND 47 k to GND 82 k to GND 0 to VDD VOUT2 (V) 0.8 1.2 1.5 1.8 2.5 3.3 0.6 to <1.6 (adjustable) 1.6 to 3.3 (adjustable) where: VREF is 0.6 V, the internal reference. ISTRING is the resistor divider string current. When R1 is determined, calculate the value of the top resistor, R2, by If the required output voltage VOUT1 (VOUT2) is in the adjustable range, from 0.6 V to less than 1.
PAGE 25
Data Sheet ADP2114 SETTING THE OSCILLATOR FREQUENCY The ADP2114 channels can be set to operate in one of the three preset switching frequencies: 300 kHz, 600 kHz, or 1.2 MHz. For 300 kHz operation, connect the FREQ pin to GND. For 600 kHz or 1.2 MHz operation, connect a resistor between the FREQ pin and GND, as shown in Table 5. An external clock can be applied to the SYNC/CLKOUT pin when configured as an input to synchronize multiple ADP2114s to the same external clock.
PAGE 26
ADP2114 Data Sheet OPERATION MODE CONFIGURATION The dual-channel ADP2114 can be configured to one of the four modes of operation by connecting the OPCFG pin as shown in Table 7. This configuration sets the current limit for each channel and enables or disables the transition to pulse skip mode at light loads. In the dual-phase configuration, the outputs of the two channels are connected together, and they generate a single dc output voltage, VOUT.
PAGE 27
Data Sheet ADP2114 EXTERNAL COMPONENTS SELECTION INPUT CAPACITOR SELECTION The input current to a buck converter is pulsating in nature. The current is zero when the high-side switch is off and approximately equal to the load current when it is on. Because this occurs at reasonably high frequencies (300 kHz to 1.2 MHz), the input bypass capacitor ends up supplying most of the high frequency current (ripple current), allowing the input power source to supply only the average (dc) current.
PAGE 28
ADP2114 Data Sheet The ADP2114 can be configured in either a 2 A/2 A or a 3 A/1 A current limit configuration and, therefore, the current limit thresholds for the two channels are different in each setting. The inductor chosen for each channel must have at least the peak output current limit of the IC in each case for robust operation during short-circuit conditions.
PAGE 29
Data Sheet ADP2114 The control loop can be broken down into the following three sections: • VOUT to VCOMP • VCOMP to IL • IL to VOUT Correspondingly, there are three transfer functions: ZCOMP ( fCROSS ) = VCOMP(s) VREF × g m × ZCOMP(s) = VOUT(s) VOUT (10) I L(s) = GCS VCOMP(s) (11) VOUT (s) = Z FILT (s) I L(s) (12) where: gm is the transconductance of the error amplifier, 550 µs. GCS is the current sense gain, 4 A/V. VOUT is the output voltage of the converter.
PAGE 30
ADP2114 Data Sheet DESIGN EXAMPLE The external component selection procedure from the Control Loop Compensation section is used for this design example. 3. L= Table 9. 2-Channel Step-Down DC-to-DC Converter Requirements Parameter Input Voltage, VIN Channel 1, VOUT1 Specification 5.0 V ±10% 3.3 V, 2 A, 1% VOUT ripple (p-p) Channel 2, VOUT2 1.8 V, 2 A, 1% VOUT ripple (p-p) Pulse-Skip Feature Enabled Therefore, when L = 3.3 µH (the closest standard value) in Equation 3, ΔIL = 0.566 A.
PAGE 31
Data Sheet ADP2114 The switching frequency (fSW) of 600 kHz, which is chosen based on the Channel 1 requirements, meets the duty cycle ranges that have been previously calculated. Therefore, this switching frequency is acceptable. In this case, the following values are substituted for the variables in Equation 18: gm = 550 µs GCS = 4A/V VREF = 0.6 V VOUT = 3.3 V COUT = 0.8 × 47 µF (capacitance derated by 20% to account for dc bias). 3. L= RCOMP = 27 kΩ. Therefore, when L = 3.
PAGE 32
ADP2114 5. Data Sheet SYSTEM CONFIGURATION Calculate the feedback loop, compensation component values by using Equation 15. Complete the following steps to further configure the ADP2114 for this design example: V H(s) = gm × GCS × REF × ZCOMP(s) × ZFILT(s) VOUT 1. In this case, the following values are substituted for the variables in Equation 18: gm = 550 µs GCS = 4 VREF = 0.6 V VOUT = 1.8 V COUT = 0.8 × (47+22) µF (capacitance derated by 20% to account for dc bias). From Equation 18, RCOMP = 22 kΩ.
PAGE 33
Data Sheet ADP2114 APPLICATION CIRCUITS VIN = 5V 10Ω 1µF 100kΩ 100kΩ 22µF EN1 VIN1 VDD EN2 VIN4 VOUT2 = 1.8V, 2A 22µF VIN3 PGOOD1 VIN6 PGOOD2 PGOOD2 3.3µH SW3 ADP2114 SW4 47µF 22µF VIN2 VIN5 SW1 PGOOD1 3.3µH VOUT1 = 3.3V, 2A SW2 PGND1 PGND3 47µF PGND2 PGND4 15kΩ SYNC FB1 FB2 V2SET V1SET 47kΩ 22kΩ FREQ OPCFG SCFG GND SYNC/CLKOUT COMP1 SS1 COMP2 SS2 10nF 10nF 27kΩ 1000pF 08143-079 8.2kΩ 1100pF fSW = 600kHz Figure 79.
PAGE 34
ADP2114 Data Sheet VIN = 5V 10Ω 1µF 100kΩ VDD EN2 VIN4 22µF EN1 VIN1 SCFG 100kΩ VIN3 PGOOD1 VIN6 PGOOD2 PGOOD2 VOUT2 = 3.3V, 1A 6.8µH SW3 ADP2114 SW4 22µF SW1 PGOOD1 6.8µH VOUT1 = 1.8V, 3A SW2 PGND1 PGND3 47µF 22µF VIN2 VIN5 47µF 100µF PGND2 PGND4 47kΩ CLKOUT FB1 FB2 V2SET V1SET 15kΩ COMP1 SS1 GND COMP2 SS2 22kΩ 10nF 8.2kΩ 10nF FREQ 20kΩ OPCFG SYNC/CLKOUT 2.4nF 08143-081 2.4nF fSW = 300kHz Figure 81. Application Circuit for 3 A/1 A Outputs VIN = 3.
PAGE 35
Data Sheet ADP2114 POWER DISSIPATION, THERMAL CONSIDERATIONS Power dissipated by the ADP2114 dual switching regulator is a major factor that affects the efficiency of the two dc-to-dc converters. The efficiency is given by The power dissipated by the regulator increases the die junction temperature, TJ, above the ambient temperature, TA. The power loss of the step-down dc-to-dc converter is approximated by TJ = TA + TR (22) where: PD is the power dissipation on the ADP2114.
PAGE 36
ADP2114 Data Sheet CIRCUIT BOARD LAYOUT RECOMMENDATIONS • • • • • • Use separate analog and power ground planes. Connect the ground reference of sensitive analog circuitry, such as output voltage divider components, to analog ground. In addition, connect the ground references of power components, such as input and output capacitors, to power ground. Connect both ground planes to the exposed pad of the ADP2114.
PAGE 37
Data Sheet ADP2114 OUTLINE DIMENSIONS 5.00 BSC SQ 0.60 MAX 0.60 MAX 25 32 1 24 0.50 BSC 3.25 3.10 SQ 2.95 EXPOSED PAD 17 TOP VIEW 1.00 0.85 0.80 0.80 MAX 0.65 TYP 12° MAX 0.30 0.25 0.18 SEATING PLANE 0.50 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 8 16 9 BOTTOM VIEW 0.25 MIN 3.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 05-23-2012-A 4.
PAGE 38
ADP2114 Data Sheet NOTES Rev.
PAGE 39
Data Sheet ADP2114 NOTES Rev.