Datasheet

ADP2108 Data Sheet
Rev. G | Page 16 of 20
OUTLINE DIMENSIONS
Figure 36. 5-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-5-3)
Dimensions shown in millimeters
Figure 37. 5-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-5)
Dimensions shown in millimeters
06-11-2012-B
A
B
C
0.657
0.602
0.546
0.355
0.330
0.304
0.280
0.250
0.220
1.060
1.020
0.980
1.490
1.450
1.410
12
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SIDE DOWN)
SIDE VIEW
0.330
0.310
0.290
0.866
REF
BALL A1
IDENTIFIER
SEATING
PLANE
0.50 BSC
COPLANARITY
0.04
0.50
BSC
100708-A
*
COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
1.60 BSC
2.80 BSC
1.90
BSC
0.95 BSC
0.20
0.08
0.60
0.45
0.30
8°
4°
0°
0.50
0.30
0.10 MAX
*
1.00 MAX
*
0.90 MAX
0.70 MIN
2.90 BSC
5 4
1 2 3
SEATING
PLANE