Datasheet

EVAL-ADP2108
Rev. A | Page 6 of 8
EVALUATION BOARD SCHEMATICS AND ARTWORK
0
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V
OUT
GND OUT
V
OUT
A
DP2108
TB3
TB4
C
OUT
10µF
L1
1µH
U1
1B
C2
A1
V
IN
C1
A2
GND
2
C
IN
4.7µF
V
IN
EN
EN
VIN SW
FBEN
TB1
TB2
G
ND IN
TB5
Figure 9. Evaluation Board Schematic of ADP2108
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Figure 10. Top Layer, Recommended Layout for TSOT
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Figure 11. Top Layer, Recommended Layout for TSOT
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Figure 12. Bottom Layer, Recommended Layout for WLCSP
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Figure 13. Bottom Layer, Recommended Layout for TSOT