Datasheet

ADP2102
Rev. B | Page 22 of 24
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Good circuit board layout is essential in obtaining the best
performance from the ADP2102. Poor circuit layout degrades
the output ripple and regulation, as well as the EMI and
electromagnetic compatibility performance.
Figure 52 and Figure 53 show the ideal circuit board layout for
the typical applications circuit shown in
Figure 48. Use this
layout to achieve the highest performance. Refer to the following
guidelines for optimum layout:
•
Use separate analog and power ground planes. Connect the
ground reference of sensitive analog circuitry, such as output
voltage divider components, to analog ground. In addition,
connect the ground references of power components, such as
input and output capacitors, to power ground. Connect both
ground planes to the exposed pad of the ADP2102.
•
Place the input capacitor as close to the PVIN pin as possible
and connect the other end to the closest power ground plane.
•
For low noise and better transient performance, a filter is
recommended between PVIN and AVIN. Place the 0.1 F,
10  low-pass input filter between the AVIN pin and the
PVIN pin, as close to AVIN as possible; or the AVIN pin can
be bypassed with a ≥1 pF capacitor to the nearest GND plane.
•
Ensure that the high current loops are as short and as wide
as possible. Make the high current path from C
IN
through L,
C
OUT
, and the PGND plane back to C
IN
as short as possible.
To accomplish this, ensure that the input and output capacitors
share a common PGND plane. In addition, make the high
current path from the PGND pin through L and C
OUT
back
to the PGND plane as short as possible. To do this, ensure
that the PGND pin of the ADP2102 is tied to the PGND
plane as close as possible to the input and output capacitors.
•
Place the feedback resistor divider network as close as possible
to the FB pin to prevent noise pickup. Try to minimize the
length of trace connecting the top of the feedback resistor
divider to the output while keeping away from the high
current traces and the switch node (LX) that can lead to
noise pickup. To reduce noise pickup, place an analog ground
plane on either side of the FB trace and make it as small as
possible to reduce the parasitic capacitance pickup.
RECOMMENDED LAYOUT
06631-041
8 mm
VOUT
COUT
PGND
VIN
9 mm
MODE
EN
FB/OUT
AGND
L1
INDUCTOR
CIN
CBP
ADP2102
Figure 51. Recommended PCB Layout of the ADP2102-FXD