Datasheet

ADP2102
Rev. B | Page 21 of 24
Output Capacitor
For transient applications, assume a droop of 0.1 V. Typically,
it takes two to three cycles for the output to settle from a load
transient because the capacitor alone supplies the load current
until the loop responds.
Under these conditions, a minimum required output
capacitance is calculated as follows:
C
OUT_MIN
= 3 ×
SWDROOP
LOAD
fV
I
×
Δ
=
6
1031.0
3.03
××
×
= 3 µF
Choose a 4.7 µF capacitor for this application.
For an instantaneous step decrease in load current, the output
capacitor required to limit the output voltage overshoot (V
OS
)
during a full load to no load transient must be determined. This
transient requires the excess energy stored in the output inductor
to be absorbed by the output capacitor with a limited overshoot
in the output voltage.
Assuming an overshoot of 50 mV for a full load transient,
C
OUT
=
2
2
2
)(
OUT
OS
OUT
OUT
VVV
IL
+
×
=
22
2
)8.1()85.1(
)6.0(H2.2
×μ
= 4.33 µF
Choose a 4.7 µF capacitor for this application.
I
rms
=
32
1
×
MAXINSW
OUT
MAXIN
OUT
VfL
VVV
_
_
)(
××
×
=
32
1
×
2.4103102.2
)8.12.4(8.1
66
××××
×
= 45 mA rms
P
COUT
= I
rms
2
× ESR = (0.045)
2
× 0.005 = 10.12 µW
Input Capacitor
Assume an input ripple of 27 mV based on 1% of V
IN_MIN.
For ceramic capacitors, the typical ESR is from 5 mΩ to 15 m.
C
IN
=
SW
OUT
IN
fESRIV ××Δ 4)/(
1
=
6
1034)005.06.0/027.0(
1
×××
= 2.2 µF
I
rms
= I
OUT
/2 = 0.3 A rms
P
CIN
= I
rms
2
× ESR = (0.3)
2
× 0.005 = 450 µW
Losses
P
SW_COND
= (R
DS (ON)_P
× D + R
DS (ON)_N
× (1 − D)) × I
OUT
2
=
(0.310 × 0.5 + 0.145 × 0.5) × (0.6)
2
= 82 mW
P
TRAN
= (V
IN
/2) × I
OUT
× (t
R
+ t
F
) × f
SW
=
(3.6/2) × 0.6 × (5 ns + 5 ns) × 3 × 10
6
= 32.4 mW
P
SW
= (C
GATE_P
+ C
GATE_N
) × V
IN
2
× f
SW
= (200 pF) ×
(3.6)
2
× 3 × 10
6
= 7.8 mW
P
L
= DCR × I
OUT
2
= 0.08 × (0.6)
2
= 28.8 mW
P
LOSS
= P
SW_COND
+ P
TRAN
+ P
SW
+ P
L
=
82 mW + 32.4 mW + 7.8 mW + 28.8 mW = 151 mW
T
JMAX
= T
A
+ θ
JA
P
LOSS
= 85°C + 54°C/W × 151 mW = 93.15°C
P
LOSS
is well below the junction temperature maximum of 125°C.