Datasheet

ADP2102
Rev. B | Page 19 of 24
SETTING THE OUTPUT VOLTAGE
The output voltage of the ADP2102-ADJ is externally set by
a resistive voltage divider from the output voltage to FB. The ratio
of the resistive voltage divider sets the output voltage, and the
absolute value of those resistors sets the divider string current. For
lower divider string currents, the small 10 nA (50 nA maximum)
FB bias current should be taken into account when calculating
resistor values. The FB bias current can be ignored for a higher
divider string current, but doing so degrades the efficiency at very
light loads.
For the ADP2102-ADJ, the equation for output voltage selection is
V
OUT
= V
FB
(1 + R
1
/R
2
) (12)
where:
V
OUT
is the output voltage.
V
FB
is the feedback voltage, 0.8 V.
R
1
is the feedback resistor from V
OUT
to FB.
R
2
is the feedback resistor from FB to GND.
For any adjustable output voltage greater than 1.875 V, a feed-
forward capacitor must be added across R1 for better transient
performance and stability. The formula for calculation of C1 is
C
FF
= 1/(2π × R1 × f
CO
/2) (13)
For example, in a 5 V to 3.3 V application, if a 4.7 µF capacitor
is used at the output, a 6.8 pF feed-forward capacitor is recom-
mended. The output capacitor value dictates the loop crossover
frequency, f
CO
. For an output capacitor of 4.7 µF, the loop crossover
frequency is 150 kHz.
The high frequency zero created by C
FF
and R1 can be very
important for transient load applications. Capacitor C
FF
provides
phase lead and functions as a speed-up capacitor to output
voltage changes, so it tends to short out R1 and improve the high
frequency response. This zero tends to produce a positive-going
bump in the phase plot. Ideally, the peak of this bump is centered
over the crossover frequency of the loop. The R1 and C
FF
zero is
located at
f
Z
= 1/(2π × R1 × C
FF
) (14)
The ADP2102-xx (where xx represents the fixed output voltage)
includes the resistive voltage divider internally, reducing the
external circuitry required. For improved load regulation, connect
the FB/OUT to the output voltage as close as possible to the load.
For more information about the ADP2102-ADJ configurations
for V
OUT
, see Table 7.
Table 7. ADP2102-ADJ Configurations for V
OUT
V
OUT
(V)
R
1
(kΩ)
R
2
(kΩ)
C
FF
(pF)
L
(μH)
C
IN
(μF)
C
OUT
(μF)
0.8 1 80.6 None 2.2 2.2 4.7
1.0 20 100 None 2.2 2.2 4.7
1.2 49.9 100 None 2.2 2.2 4.7
1.25 56.2 100 None 2.2 2.2 4.7
1.375 71.5 100 None 2.2 2.2 4.7
1.5 88.7 100 None 2.2 2.2 4.7
1.8 124 100 None 2.2 2.2 4.7
1.875 133 100 None 2.2 2.2 4.7
2.0 150 100 15 2.2 2.2 4.7
2.5 215 100 10 2.2 2.2 4.7
3.0 274 100 8.2 2.2 2.2 4.7
3.3 316 100 6.8 2.2 2.2 4.7
EFFICIENCY CONSIDERATIONS
Efficiency is defined as the ratio of output power to input power.
The high efficiency of the ADP2102 has two distinct advantages.
First, only a small amount of power is lost in the dc-to-dc converter
package that reduces thermal constraints. In addition, high effi-
ciency delivers the maximum output power for the given input
power, extending battery life in portable applications.
Following are the four major sources of power loss in dc-to-dc
converters like the ADP2102:
• Power switch conduction losses
• Inductor losses
• Switching losses
• Transition losses
Power Switch Conduction Losses
Power switch conduction losses are caused by the flow of output
current through the P-channel power switch and the N-channel
synchronous rectifier, which have internal resistances (R
DS(ON)
)
associated with them. The amount of power loss can be approxi-
mated by
P
SW_COND
= (R
DS (ON)_P
× D + R
DS (ON)_N
× (1 − D)) × I
OUT
2
(15)
where D = V
OUT
/V
IN
.
The internal resistance of the power switches increases with
temperature but decreases with higher input voltage.
Figure 24
in the
Typical Performance Characteristics section shows the
change in R
DS (ON)
vs. input voltage, and Figure 25 shows the change
in R
DS (ON)
vs. temperature for both power devices.