Datasheet

ADP1882/ADP1883
Rev. 0 | Page 34 of 40
OUTPUT CAPACITORS
ARE MOUNTED ON THE
RIGHTMOST AREA OF
THE EVB, WRAPPING
BACK AROUND TO THE
MAIN POWER GROUND
PLANE, WHERE IT MEETS
WITH THE NEGATIVE
TERMINALS OF THE
INPUT CAPACITORS.
INPUT CAPACITORS
ARE MOUNTED CLOSE
TO DRAIN OF Q1/Q2
AND SOURCE OF Q3/Q4.
BYPASS POWER CAPACITOR (C1)
FOR VDD BIAS DECOUPLING AND
HIGH FREQUENCY CAPACITOR
(C2) AS CLOSE AS POSSIBLE TO
THE IC.
SENSITIVE ANALOG
COMPONENTS
LOCATED FAR
FROM THE NOISY
POWER SECTION.
SEPARATE ANALOG GROUND
PLANE FOR THE ANALOG
COMPONENTS (THAT IS,
COMPENSATION AND
FEEDBACK RESISTORS).
08901-083
Figure 84. Overall Layout of the ADP1882 High Current Evaluation Board
08901-084
Figure 85. Layer 2 of Evaluation Board