Datasheet

ADP1882/ADP1883
Rev. 0 | Page 33 of 40
LAYOUT CONSIDERATIONS
The performance of a dc-to-dc converter depends highly on how
the voltage and current paths are configured on the printed
circuit board (PCB). Optimizing the placement of sensitive
analog and power components are essential to minimize output
ripple, maintain tight regulation specifications, and reduce
PWM jitter and electromagnetic interference.
Figure 83 shows the schematic of a typical ADP1882/ADP1883
used for a high power application. Blue traces denote high current
pathways. VIN, PGND, and V
OUT
traces should be wide and
possibly replicated, descending down into the multiple layers.
Vias should populate, mainly around the positive and negative
terminals of the input and output capacitors, alongside the
source of Q1/Q2, the drain of Q3/Q4, and the inductor.
HIGH VOLTAGE INPUT
V
IN
= 12V
HIGH VOLTAGE INPUT
V
DD
= 5V
MURATA: (HIGH VOLTAGE INPUT CAPACITORS)
22µF, 25V, X7R, 1210 GRM32ER71E226KE15 L
PANASONIC: (OUTPUT CAPACITORS)
270µF SP-SERIES, 4V, 7m EEFUE0G271LR
INFINEON MOSFETs (NO CONNECTION FOR Q2/Q4:
BSC042N03MS G (LOWER SIDE)
BSC080N03MS G (UPPER SIDE)
WURTH INDUCTORS:
1µH, 3.3m, 20A 7443552100
R5
100k
Q3 Q4
Q1 Q2
C12
100nF
V
OUT
= 1.8V, 15A
C3
22µF
C4
22µF
C5
22µF
C6
22µF
C7
22µF
C8
N/A
C23
270µF
+
C24
270µF
+
C22
270µF
+
C21
270µF
+
C20
270µF
+
C14 TO C19
N/A
+
1.0µH
R6
2
C13
1.5nF
R1 18.75k
R2
15k
R4
0
V
OUT
1
VIN
10
BST
2
COMP/EN
9
SW
3
FB
8
DRVH
4
GND
7
PGND
5
VDD
6
DRVL
ADP1882/
ADP1883
C
C
700pF
C
F
70pF
R
C
38.1k
C1
1µF
C2
0.1µF
JP1
08901-082
Figure 83. ADP1882 High Current Evaluation Board Schematic (Blue Traces Indicate High Current Paths)