Datasheet

ADP1877 Data Sheet
Rev. D | Page 8 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1EN1
2SYNC
3VIN
4VCCO
5VDL
6
A
GND
7FREQ
8EN2
24 SW1
NOTES
1. CONNECT THE BOTTOM EXPOSED PAD OF THE
LFCSP PACKAGE TO SYSTEM AGND PLANE.
23 DH1
22 PGND1
21 DL1
20 DL2
19 PGND2
18 DH2
17 SW2
9
TRK
2
10
FB2
11
COMP2
12
RAMP2
13
SS2
14
PGOOD2
15
ILIM2
16
BST2
32
TRK1
31
FB1
30
COMP1
29
RAMP1
28
SS1
27
PGO
OD1
26
ILIM1
25
BST1
TOP VIEW
(Not to Scale)
ADP1877
08299-004
Figure 4. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 EN1
Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 controller, and drive it low to turn off. Tie
EN1 to VIN for automatic startup. For a precision UVLO, put an appropriately sized resistor divider from VIN to
AGND, and tie the midpoint to this pin.
2 SYNC
Frequency Synchronization Input. Accepts an external signal between 1× and 2.3× of the internal oscillator
frequency, f
OSC
, set by the FREQ pin. The controller operates in forced PWM when a signal is detected at SYNC or
when SYNC is high. The resulting switching frequency is ½ of the SYNC frequency. When SYNC is low or left
floating, the controller operates in pulse skip mode.
3 VIN
Connect to Main Power Supply. Bypass with a 1 µF or larger ceramic capacitor connected as close to this pin as
possible and PGND.
4 VCCO
Output of the Internal Low Dropout Regulator (LDO). The internal circuitry and gate drivers are powered from
VCCO. Bypass VCCO to AGND with a 1 F or larger ceramic capacitor. The VCCO output is always active, even
during fault conditions and cannot be turned off even if EN1/EN2 is low. For operations at VIN below 5 V, VIN can
be jumped to VCCO. Do not use the LDO to power other auxiliary system loads.
5 VDL
Power Supply for the Low-Side Driver. Bypass VDL to PGND with a 1 µF or greater ceramic capacitor. Connect
VCCO to VDL.
6 AGND Analog Ground.
7 FREQ
Sets the desired operating frequency between 200 kHz and 1.5 MHz with one resistor between FREQ and AGND.
See Table 4 for more details. Connect FREQ to AGND for a preprogrammed 300 kHz or FREQ to VCCO for a 600 kHz
operating frequency.
8 EN2
Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 controller, and drive it low to turn off. Tie
EN2 to VIN for automatic startup. For a precision UVLO, put an appropriately sized resistor divider from VIN to
AGND, and tie the midpoint to this pin.
9 TRK2
Tracking Input for Channel 2. If the tracking function is not used, it is recommended to connect TRK2 to VCCO
through a resistor higher than 1 MΩ, or simply connect TRK2 between 0.7 V and 2 V to reduce the bias current
going into the TRK2 pin.
10 FB2 Output Voltage Feedback for Channel 2. Connect to Channel 2 via a resistor divider.
11 COMP2
Compensation Node for Channel 2. Output of Channel 2 error amplifier. Connect a series resistor-capacitor
network from COMP2 to AGND to compensate the regulation control loop.
12 RAMP2
Programmable Current Setting for Slope Compensation of Channel 2. Connect a resistor from RAMP2 to VIN. The
voltage at RAMP2 is 0.2 V.
13 SS2
Soft Start Input for Channel 2. Connect a capacitor from SS2 to AGND to set the soft start period. This node is
internally pulled up to 3.2 V through a 6.5 µA current source.