Datasheet

Data Sheet ADP1877
Rev. D | Page 25 of 32
PCB LAYOUT GUIDELINE
In any switching converter, there are some circuit paths that
carry high dI/dt, which can create spikes and noise. Some
circuit paths are sensitive to noise, while other circuits carry
high dc current and can produce significant IR voltage drops.
The key to proper PCB layout of a switching converter is to
identify these critical paths and arrange the components and
the copper area accordingly. When designing PCB layouts,
be sure to keep high current loops small. In addition, keep
compensation and feedback components away from the switch
nodes and their associated components.
The following is a list of recommended layout practices for the
synchronous buck controller, arranged by decreasing order of
importance.
MOSFETS, INPUT BULK CAPACITOR, AND BYPASS
CAPACITOR
The current waveform in the top and bottom FETs is a pulse
with very high dI/dt; therefore, the path to, through, and from
each individual FET should be as short as possible, and the two
paths should be commoned as much as possible. In designs that
use a pair of D-Pak or a pair of SO-8 FETs on one side of the
PCB, it is best to counter-rotate the two so that the switch node
is on one side of the pair, and the high-side drain can be
bypassed to the low side source with a suitable ceramic bypass
capacitor, placed as close as possible to the FETs. This minimizes
the inductance around this loop through the FETs and
capacitor. The recommended bypass ceramic capacitor values
range from 1 µF to 22 µF, depending upon the output current.
This bypass capacitor is usually connected to a larger value bulk
filter capacitor and should be grounded to the PGNDx plane.
HIGH CURRENT AND CURRENT SENSE PATHS
Part of the ADP1877 architecture is sensing the current across
the low-side FET between the SWx and PGNDx pins. The
switching GND currents of one channel creates noise and can
be picked up by the other channel. It is essential to keep the
SW1/SW2 and PGND1/PGND2 traces as short as possible and
placed very close to the FETs to achieve accurate current
sensing. The following schematic illustrates the proper
connection technique for the SW1/SW2, PGND1/PGND2, and
PGNDx plane. Note that PGND1 and PGND2 are only jointed
at the PGND plane.
ADP1877
DH1
SW1
M2
L1
V
OUT1
VIN
M1
PGND PLANE
COUT1CIN1
C
DECOUPLE1
M3
L2
V
OUT2
VIN
M4
COUT2CIN2
C
DECOUPLE2
23
24
21
22
19
20
17
18
PGND2
DL2
SW2
DH2
DL1
PGND1
08299-017
Figure 40. Grounding Technique for Two Channels
SIGNAL PATHS
The negative terminals of AGND, VIN bypass, compensation
components, soft start capacitor, and the bottom end of the
output feedback divider resistors should be tied to an almost
isolated small AGND plane. These connections should attach
from their respective pins to the AGND plane; these
connections should be as short as possible. No high current or
high dI/dt signals should be connected to this AGND plane.
The AGND area should be connected through one wide trace to
the negative terminal of the output filter capacitors.
PGND PLANE
The PGNDx pin handles a high dI/dt gate drive current returning
from the source of the low side MOSFET. The voltage at this pin
also establishes the 0 V reference for the overcurrent limit
protection function and the ILIMx pin. A PGND plane should
connect the PGNDx pin and the VDL bypass capacitor, 1 µF,
through a wide and direct path to the source of the low side
MOSFET. The placement of CIN is critical for controlling
ground bounce. The negative terminal of CIN must be placed
very close to the source of the low-side MOSFET.
FEEDBACK AND CURRENT-LIMIT SENSE PATHS
Avoid long traces or large copper areas at the FBx and ILIMx
pins, which are low signal level inputs that are sensitive to
capacitive and inductive noise pickup. It is best to position any
series resistors and capacitors as close as possible to these pins.
Avoid running these traces close and/or parallel to high dI/dt
traces.