Datasheet
Data Sheet ADP1877
Rev. D | Page 23 of 32
SWITCHING NOISE AND OVERSHOOT REDUCTION
In any high speed step-down regulator, high frequency noise
(generally in the range of 50 MHz to 100 MHz) and voltage
overshoot are always present at the gate, the switch node (SW),
and the drains of the external MOSFETs. The high frequency
noise and overshoot are caused by the parasitic capacitance,
C
GD
, of the external MOSFET and the parasitic inductance of
the gate trace and the packages of the MOSFETs. When the high
current is switched, electromagnetic interference (EMI) is
generated, which can affect the operation of the surrounding
circuits. To reduce voltage ringing and noise, it is required to
add an RC snubber between SW and PGND for applications with
more than 10 A output current, as illustrated in Figure 35.
Snubbers may also be needed in applications where the duty
cycle in one of the channels is higher than or equal to 50%.
In most applications, R
SNUB
is typically 2 Ω to 4 Ω, and C
SNUB
typically 1.2 nF to 3 nF.
R
SNUB
can be estimated by
OSS
MOSFET
SNUB
C
L
R 2
≅
And C
SNUB
can be estimated by
OSSSNUB
CC ≅
where
:
L
MOSFET
is the total parasitic inductance of the high-side and
low-side MOSFETs, typically 3 nH, and is package dependent.
C
OSS
is the total output capacitance of the high-side and low-
side MOSFETs given in the MOSFET data sheet.
The size of the RC snubber components need to be chosen
correctly to handle the power dissipation. The power dissipated
in R
SNUB
is
SWSNUB
IN
SNUB
fCVP
××=
2
In most applications, a component size 0805 for R
SNUB
is sufficient.
However, the use of an RC snubber reduces the overall efficiency,
generally by an amount in the range of 0.1% to 0.5%. The RC
snubber cannot reduce the voltage overshoot. A resistor, shown
as R
RISE
in Figure 35, at the BSTx pin helps to reduce overshoot
and is generally between 2 Ω and 4 Ω. Adding a resistor in
series, typically between 2 Ω and 4 Ω, with the gate driver also
helps to reduce overshoot. If a gate resistor is added, then R
RISE
is not needed.
DH1
SW1
ILIM1
DL1
PGND1
M2
M1
L
VOUT
COUTx
R
SNUB
C
SNUB
R
RISE
BST1
VDL
R
ILIM1
ADP1877
(CHANNEL 1)
VIN
08299-012
Figure 35. Application Circuit with a Snubber
VOLTAGE TRACKING
The ADP1877 includes a tracking feature that tracks a master
voltage. This feature is especially important when the ADP1877
is powering separate power supply voltages on a single integrated
circuit, such as the core and I/O voltages of a DSP or microcon-
troller. In these cases, improper sequencing can cause damage
to the load.
In all tracking configurations, the output can be set as low as 0.6 V
for a given operating condition. The soft start time setting of
the master voltage should be longer than the soft start of the
slave voltage. This forces the rise time of the master voltage to
be imposed on the slave voltage. If the soft start setting of the
slave voltage is longer, the slave comes up more slowly, and the
tracking relationship is not seen at the output.
Two tracking configurations are possible with the ADP1877:
coincident and ratiometric trackings. Full time DDR termination is
not recommended when using these tracking features.
COINCIDENT TRACKING
The most common application is coincident tracking, used in
core vs. I/O voltage sequencing and similar applications.
Coincident tracking limits the slave output voltage to be the
same as the master voltage until it reaches regulation. Connect
the slave TRK input to a resistor divider from the master voltage
that is the same as the divider used on the slave FB pin. This
forces the slave voltage to be the same as the master voltage. For
coincident tracking, use R
TRKT
= R
TOP
and R
TRKB
= R
BOT
, as shown
in Figure 37.
TIME
SLAVE VOLTAGE
MASTER VOLTAGE
VOLTAGE (V)
08299-013
Figure 36. Coincident Tracking
C
SS1
100nF
C
SS2
20nF
3.3
V
V
OUT1_MASTER
FB1
EN
R
BOT
10kΩ
FB2
SS1
ADP1877
EN1 EN2
SS2
V
CCO
TRK1
TRK2
R
TOP
20kΩ
1.8V
V
OUT2_SLAVE
R
TRKB
10kΩ
R
TRKT
20kΩ
1.1V
10kΩ
45.3kΩ
08299-014
1MΩ
Figure 37. Example of a Coincident Tracking Circuit