Datasheet

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Dual Output Synchronous Buck

PWM Controller

Data Sheet

ADP1877

Rev. D

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FEATURES

Input voltage range: 2.75 V to 14.5 V

Output voltage range: 0.6 V to 90% V

Maximum output current greater than 25 A per channel

Programmable frequency: 200 kHz to 1.5 MHz

Flex-Mode architecture with integrated drivers

180° phase shift minimizes input ripple current and required

input capacitance

±0.85% output voltage accuracy −40°C to +85°C

Integrated boost diodes

Pulse skip high efficiency mode under light load

Power good with internal pull-up resistor

Overvoltage and overcurrent limit protection

Thermal overload protection

Input undervoltage lockout (UVLO)

Externally adjustable soft start, slope compensation and

current sense gain

Independent precision enable inputs

Synchronization input

Suitable for any output capacitors

Available in 32-lead 5 mm × 5 mm LFCSP

APPLICATIONS

Set top boxes

Printers

Communication infrastructure

Distributor power dc systems

Industrial and instrumentation

GENERAL DESCRIPTION

The ADP1877 is a Flex-Mode™ (proprietary architecture of

Analog Devices, Inc.), dual-channel, step-down switching

controller with integrated drivers that drive N-channel

synchronous power MOSFETs. The two PWM outputs are

phase shifted 180°, which reduces the input RMS current, thus

minimizing required input capacitance.

The boost diodes are built into the ADP1877, thus lowering the

overall system cost and component count. The ADP1877 can

be set to operate in pulse skip high efficiency mode under light

load or in PWM continuous conduction mode.

The ADP1877 includes externally adjustable soft start, output

overvoltage protection, externally adjustable current limit,

power good, and a programmable oscillator frequency that

ranges from 200 kHz to 1.5 MHz. The ADP1877 provides an

output voltage accuracy of ±0.85% from −40°C to +85°C and

±1.5% from −40°C to 125°C in junction temperature. This part

can be powered from a 2.75 V to 14.5 V supply, operates over

the −40

C to +125

C junction temperature range, and is availa-

ble in a 32-lead 5 mm × 5 mm LFCSP package.

RAMP1

AMP1

VIN

DH1

BST1

SW1

ILIM1

FB1

DL1

PGND1

RAMP2

DH2

BST2

SW2

ILIM2

FB2

DL2

PGND2

EN1

EN2

VDL

VCCO

PGOOD1

PGOOD2

TRK1

TRK2

SYNC

FREQ

COMP1

COMP2

SS1

SS2

AGND

CSG1

TOP1

BOT1

CSG2

TOP2

VOUT1

VOUT2

VIN

BOT2

RAMP2

08299-001

Figure 1. Typical Operation Circuit

0.01 0.1 1 10 100

100

= 3.3V PSM

= 3.3V PWM

= 1.8V PSM

= 1.8V PWM

= 12V, 300kHz

08299-002

EFFICIENCY (%)

LOAD (A)

Figure 2. Efficiency Plot of Figure 42, 20 A Output

Summary of content (32 pages)

PAGE 1
Input voltage range: 2.75 V to 14.5 V Output voltage range: 0.6 V to 90% VIN Maximum output current greater than 25 A per channel Programmable frequency: 200 kHz to 1.5 MHz Flex-Mode architecture with integrated drivers 180° phase shift minimizes input ripple current and required input capacitance ±0.
PAGE 2
ADP1877 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Setting the Current Limit .......................................................... 17 Applications ....................................................................................... 1 Accurate Current-Limit Sensing .............................................. 18 General Description .......................................................................
PAGE 3
Data Sheet ADP1877 SPECIFICATIONS All limits at temperature extremes are guaranteed via correlation using standard statistical quality control. VIN = 12 V. The specifications are valid for TJ = −40°C to +125°C, unless otherwise specified. Typical values are at TA = 25°C. Table 1.
PAGE 4
ADP1877 Data Sheet Parameter LOGIC INPUTS EN1, EN2 EN1, EN2 Hysteresis EN1, EN2 Input Leakage Current SYNC Logic Input Low SYNC Logic Input High SYNC Input Leakage Current GATE DRIVERS DH Rise Time DH Fall Time DL Rise Time DL Fall Time DH to DL Dead Time DH or DL Driver RON, Sourcing Current1 Symbol DH or DL Driver RON, Tempco DH or DL Driver RON, Sinking Current1 DH Maximum Duty Cycle DH Maximum Duty Cycle Minimum DH On Time Minimum DH Off Time Minimum DL On Time COMP VOLTAGE RANGE COMP Pulse Skip Thr
PAGE 5
Data Sheet Parameter PGOOD PGOOD Pull-up Resistor PGOOD Delay Overvoltage or Undervoltage Minimum Duration ILIM1, ILIM2 Threshold Voltage1 ILIM1, ILIM2 Output Current Current Sense Blanking Period INTEGRATED RECTIFIER (BOOST DIODE) RESISTANCE ZERO CURRENT CROSS OFFSET (SW TO PGND)1 1 2 ADP1877 Symbol Conditions RPGOOD Internal pull-up resistor to VCCO Min Typ Max 12.5 12 12 This is the minimum duration required to trip the PGOOD signal.
PAGE 6
ADP1877 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2.
PAGE 7
Data Sheet ADP1877 SIMPLIFIED BLOCK DIAGRAM VIN THERMAL SHUTDOWN VCCO AGND UVLO 0.6V EN1_SW EN2_SW LOGIC + – EN1 OV 0.6V UV REF LDO + EN2 VCCO – OV1 LOGIC SYNC UV1 PH1 1MΩ FREQ COMP1 FB1 TRK1 SS1 FB1 0.6V – + + Gm + PGOOD1 + – OV ERROR AMPLIFIER 10kΩ DUPLICATE FOR CHANNEL 2 PH2 OSCILLATOR + – UV VCCO BST1 SYNC EN1_SW VREF = 0.6V – 6.5µA FAULT 1kΩ 3.2V LOGIC 0.
PAGE 8
ADP1877 Data Sheet 32 31 30 29 28 27 26 25 TRK1 FB1 COMP1 RAMP1 SS1 PGOOD1 ILIM1 BST1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 PIN 1 INDICATOR ADP1877 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 SW1 DH1 PGND1 DL1 DL2 PGND2 DH2 SW2 NOTES 1. CONNECT THE BOTTOM EXPOSED PAD OF THE LFCSP PACKAGE TO SYSTEM AGND PLANE. 08299-004 TRK2 FB2 COMP2 RAMP2 SS2 PGOOD2 ILIM2 BST2 9 10 11 12 13 14 15 16 EN1 SYNC VIN VCCO VDL AGND FREQ EN2 Figure 4. Pin Configuration Table 3.
PAGE 9
Data Sheet Pin No. 14 Mnemonic PGOOD2 15 ILIM2 16 BST2 17 SW2 18 DH2 19 PGND2 20 DL2 21 DL1 22 PGND1 23 DH1 24 SW1 25 BST1 26 ILIM1 27 PGOOD1 28 SS1 29 RAMP1 30 COMP1 31 32 FB1 TRK1 33 Bottom exposed pad ADP1877 Description Open-drain power-good indicator logic output with an internal 12 kΩ resistor connected between PGOOD2 and VCCO. PGOOD2 is pulled to ground when the Channel 2 output is outside the regulation window. An external pull-up resistor is not required.
PAGE 10
ADP1877 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.06 100 VOUT = 3.3V AT 1A LOAD 90 PSM LINE REGULATION (%) EFFICIENCY (%) 70 60 PWM 50 40 30 20 0.1 1 100 10 0.02 LOAD (A) 0 08299-023 0 0.01 0.03 0.01 VIN = 12V VOUT = 3.3V 600kHz 10 0.04 6 14 0 80 –0.05 VOUT = 1.05V PSM 70 60 ∆ VCCO (V) EFFICIENCY (%) 12 Figure 8. Line Regulation of Figure 42 VIN = 3V VOUT = 1.8V PWM 90 10 VIN (V) Figure 5. Efficiency Plot of Figure 41, 10 A Output 100 8 08299-026 80 0.
PAGE 11
Data Sheet ADP1877 6 5 OUTPUT RESPONSE 1 VCCO (V) 4 3 OUTPUT STEP LOAD 0.5A TO 0.8A 2 4 1 0 1 2 3 4 5 6 VIN (V) CH1 20mV 08299-029 0 Figure 11. VCCO vs. VIN CH4 500mA Ω M100µs A CH4 750mA 08299-037 VIN = 3V VOUT = 1.8V Figure 14. Step Load Transient of Figure 44 SW1 1 DH1 1 SW2 DL1 2 2 VOUT1 3 3 IL1 4 SYNC 600kHz CH2 10V M1µs A CH1 5.60V CH1 5V CH3 1V Figure 12. An Example of Synchronization, fSW = 600 kHz CH2 5V CH4 1A Ω M1ms A CH1 2.
PAGE 12
ADP1877 Data Sheet 2.0 VIN = 12V; REFERENCED AT 25°C 1.5 1.0 CHANGE IN fOSC (%) SW VOUT (CH3) EN CH2 2V CH4 1V M10ms A CH2 1.52V –1.0 –2.5 –40 08299-040 CH1 10V –0.5 –2.0 CSS = 100nF CH3 1V 0 –1.5 SS (CH4) 3 2 4 0.5 –15 10 35 60 85 110 135 TEMPERATURE (°C) Figure 17. Enable Function 08299-031 1 Figure 20. fOSC vs.
PAGE 13
Data Sheet ADP1877 THEORY OF OPERATION The ADP1877 is a current mode (using ADI proprietary Flex-Mode architecture), dual-channel, step-down switching controller with integrated MOSFET drivers that drive N-channel synchronous power MOSFETs. The two outputs are phase shifted 180°. This reduces the input RMS current, thus minimizing required input capacitance. The ADP1877 can be set to operate in pulse skip high efficiency mode under light load or in forced PWM.
PAGE 14
ADP1877 Data Sheet MODE OF OPERATION The SYNC pin is a multifunctional pin. PWM mode is enabled when SYNC is connected to VCCO or a high logic. With SYNC connected to ground or left floating, pulse skip mode is enabled. Switching SYNC from low to high or high to low on the fly causes the controller to transition from forced PWM to pulse skip mode or pulse skip mode to forced PWM, respectively, in two clock cycles. DH1 1 DL1 2 OUTPUT RIPPLE 3 Table 5.
PAGE 15
Data Sheet ADP1877 VIN = 2.75V TO 5.5V SYNCHRONOUS RECTIFIER AND DEAD TIME When the bias input voltage, VIN, is less than the undervoltage lockout (UVLO) threshold, the switch drivers stay inactive. When VIN exceeds the UVLO threshold, the switchers start switching. INTERNAL LINEAR REGULATOR The internal linear regulator is low dropout (LDO), meaning it can regulate its output voltage, VCCO. VCCO powers up the internal control circuitry and provides power for the gate drivers.
PAGE 16
ADP1877 Data Sheet SHUTDOWN CONTROL When the output is shorted or the output current exceeds the current limit set by the RILIM resistor for eight consecutive cycles, the ADP1877 shuts off both the high-side and low-side drivers and restarts the soft start sequence every 10 ms, which is known as hiccup mode. The SS node discharges to zero through an internal 1 kΩ resistor during an overcurrent or short-circuit event.
PAGE 17
Data Sheet ADP1877 APPLICATIONS INFORMATION SETTING THE OUTPUT VOLTAGE The output voltage is set using a resistive voltage divider from the output to FB. The voltage divider divides down the output voltage to the 0.6 V FB regulation voltage to set the regulation output voltage. The output voltage can be set to as low as 0.6 V and as high as 90% of the power input voltage. The maximum input bias current into FB is 100 nA. For a 0.
PAGE 18
ADP1877 Data Sheet VIN ACCURATE CURRENT-LIMIT SENSING RDSON of the MOSFET can vary by more than 50% over the temperature range. Accurate current limit sensing can be achieved by adding a current sense resistor from the source of the low-side MOSFET to PGND. Make sure that the power rating of the current sense resistor is adequate for the application. Apply the above equation and calculate RILIM by replacing RDSON_MAX with RSENSE.
PAGE 19
Data Sheet ADP1877 Table 6. CS Gain Setting Selection Table for Some Popular Configurations RDSON (mΩ) 1.5 2 2 3 5 7 10 15 18 20 25 30 40 60 80 100 120 ACS = 3 Load (A) 25 25 20 20 15 10 10 8 8 7 5 5 5 3 2 2 2 VCS Min (V) 0.73 0.73 0.73 0.72 0.71 0.72 0.70 0.69 0.68 0.68 0.69 0.68 0.65 0.66 0.67 0.65 0.63 VCS Max (V) 0.9 0.9 0.9 1.0 1.0 1.0 1.1 1.2 1.3 1.2 1.2 1.3 1.4 1.4 1.3 1.4 1.6 ACS = 6 VCS Min (V) 0.71 0.70 0.71 0.69 0.68 0.68 0.65 0.63 0.61 0.61 0.63 0.60 ACS = 12 VCS Max (V) 1.01 1.10 1.
PAGE 20
ADP1877 Data Sheet BOOST CAPACITOR SELECTION To lower system component count and cost, the ADP1877 has a built-in rectifier (equivalent to the boost diode) between VCCO and BSTx. Choose a boost ceramic capacitor with values between 0.1 μF and 0.22 μF, which provides the current for the high-side driver during switching. INDUCTOR SELECTION The output LC filter smoothes the switched voltage at SWx.
PAGE 21
Data Sheet ADP1877 MOSFET SELECTION The choice of MOSFET directly affects the dc-to-dc converter performance. A MOSFET with low on resistance reduces I2R losses, and low gate charge reduces transition losses. The MOSFET should have low thermal resistance to ensure that the power dissipated in the MOSFET does not result in excessive MOSFET die temperature. The high-side MOSFET carries the load current during on time and usually carries most of the transition losses of the converter.
PAGE 22
ADP1877 Data Sheet Then the power loss in the low-side MOSFET is Because the zero produced by the ESR of the output capacitor is not needed to stabilize the control loop, the ESR is ignored for analysis. Then ZFILTER is given by PLS = PCLS + PBODYDIODE Note that MOSFET, RDSON, increases with increasing temperature with a typical temperature coefficient of 0.4%/oC.
PAGE 23
Data Sheet ADP1877 SWITCHING NOISE AND OVERSHOOT REDUCTION VOLTAGE TRACKING In any high speed step-down regulator, high frequency noise (generally in the range of 50 MHz to 100 MHz) and voltage overshoot are always present at the gate, the switch node (SW), and the drains of the external MOSFETs. The high frequency noise and overshoot are caused by the parasitic capacitance, CGD, of the external MOSFET and the parasitic inductance of the gate trace and the packages of the MOSFETs.
PAGE 24
ADP1877 Data Sheet The ratio of the slave output voltage to the master voltage is a function of the two dividers. As the master voltage rises, the slave voltage rises identically. Eventually, the slave voltage reaches its regulation voltage, where the internal reference takes over the regulation while the TRKx input continues to increase and thus removes itself from influencing the output voltage.
PAGE 25
Data Sheet ADP1877 PCB LAYOUT GUIDELINE VIN In any switching converter, there are some circuit paths that carry high dI/dt, which can create spikes and noise. Some circuit paths are sensitive to noise, while other circuits carry high dc current and can produce significant IR voltage drops. The key to proper PCB layout of a switching converter is to identify these critical paths and arrange the components and the copper area accordingly.
PAGE 26
ADP1877 Data Sheet SWITCH NODE The switch node is the noisiest place in the switcher circuit with large ac and dc voltages and currents. This node should be wide to keep resistive voltage drop down. To minimize the generation of capacitively coupled noise, the total area should be small. Place the FETs and inductor close together on a small copper plane to minimize series resistance and keep the copper area small.
PAGE 27
Data Sheet ADP1877 TYPICAL OPERATING CIRCUITS 330pF 66.5kΩ 47pF VIN = 10V TO 14V M1 RTOP1 45.3kΩ 845kΩ VCCO RBOT1 10kΩ CIN1 100nF RILIM1 4kΩ 2Ω VCCO 26 25 BST1 VIN 4 27 ILIM1 SYNC 3 28 PGOOD1 2 29 SS1 EN1 30 RAMP1 1 31 FB1 TRK1 32 COMP1 1MΩ L1 0.1µF COUT11 COUT12 VOUT1 3.3V 10A M2 SW1 24 DH1 23 1µF PGND1 RCSG1 4kΩ 22 1µF DL1 21 1µF 8 EN2 SW2 17 11 12 13 845kΩ 10 1MΩ VCCO 36.5kΩ 15 16 RBOT2 10kΩ CIN2 RILIM2 4kΩ L2 M4 COUT21 0.1µF COUT22 VOUT2 1.
PAGE 28
ADP1877 Data Sheet 2.2nF 18.7kΩ 220pF VIN = 10V TO 14V RTOP1 20kΩ RILIM1 3.7kΩ 2Ω FB1 COMP1 RAMP1 28 27 26 25 BST1 29 ILIM1 30 SS1 31 PGOOD1 32 TRK1 1MΩ 0.1µF COUT11 4Ω SW1 24 EN1 2 SYNC 3 VIN 4 VCCO 5 VDL 6 AGND PGND2 19 7 FREQ DH2 18 8 EN2 SW2 17 DH1 23 RDH1 3Ω 1µF PGND1 22 1µF DL1 21 COMP2 RAMP2 SS2 PGOOD2 ILIM2 BST2 10 11 12 13 14 15 16 845kΩ FB2 9 1MΩ VCCO 3.9nF DL2 20 TRK2 VCCO ADP1877 12.7kΩ 1.
PAGE 29
Data Sheet ADP1877 820pF 22.6kΩ 68pF VIN = 10V TO 14V M1A RTOP1 73.2kΩ 698kΩ VCCO RBOT1 10kΩ CIN1 100nF RILIM1 2.8kΩ 3Ω 25 BST1 VCCO 26 ILIM1 VIN 4 27 PGOOD1 3 28 SS1 SYNC 29 RAMP1 2 30 FB1 EN1 31 COMP1 1 32 TRK1 1MΩ L1 0.1µF COUT1 VOUT1 5V 5A M1B SW1 24 DH1 23 1µF RCSG1 22kΩ PGND1 22 1µF DL1 21 1µF 8 EN2 SW2 17 10 11 12 13 698kΩ 9 15 16 CIN2 RILIM2 2.8kΩ COUT2 VOUT2 1.8V 5A RCSG2 22kΩ RTOP2 20kΩ L1: 2µH, 744310200, WURTH ELEKTRONIK L2: 1.
PAGE 30
ADP1877 Data Sheet 1.8nF 5.34kΩ 33pF VIN = 3V TO 5.5V M1 RTOP1 73.2kΩ 121kΩ VCCO RBOT1 10kΩ CIN1 100nF RILIM1 4.99kΩ 5Ω 25 BST1 VCCO 26 ILIM1 VIN 4 27 PGOOD1 3 28 SS1 SYNC 29 RAMP1 2 30 COMP1 EN1 31 FB1 1 32 TRK1 1MΩ L1 0.1µF COUT1 VOUT1 1.05V 1.8A M2 SW1 24 DH1 23 1µF RCSG1 47kΩ PGND1 22 1µF DL1 21 1µF 8 EN2 SW2 17 10 11 13 14 15 16 L2 M4 COUT2 VOUT2 1.8V 1.8A 100nF RCSG2 47kΩ RTOP2 20kΩ CIN1, CIN2: 4.
PAGE 31
Data Sheet ADP1877 OUTLINE DIMENSIONS 5.10 5.00 SQ 4.90 32 25 0.50 BSC 0.80 0.75 0.70 0.50 0.40 0.30 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 3.65 3.50 SQ 3.45 EXPOSED PAD 17 TOP VIEW PIN 1 INDICATOR 1 24 9 BOTTOM VIEW 0.25 MIN 3.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 04-02-2012-A PIN 1 INDICATOR 0.30 0.25 0.18 Figure 45.