Datasheet
Data Sheet ADP1874/ADP1875
Rev. A | Page 7 of 44
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VIN
1
COMP
2
EN
3
FB
4
BST
16
SW
15
DRVH
14
PGND
13
GND
5
DRVL
12
RES
6
PGOOD
11
VREG
7
SS
10
VREG_IN
8
TRACK
9
ADP1874/
ADP1875
TOP VIEW
(Not to Scale)
09347-003
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin
No. Mnemonic Description
1 VIN High-Side Input Voltage. Connect VIN to the drain of the upper side MOSFET.
2 COMP Output of the Error Amplifier. Connect the compensation network between this pin and AGND to achieve stability (see the
Compensation Network section).
3 EN Connect to VREG to Enable IC. When pulled down to AGND externally, disables the IC.
4 FB Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected.
5 GND Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground plane
(see the Layout Considerations section).
6 RES Current Sense Gain Resistor (External). Connect a resistor between the RES pin and GND (Pin 5).
7 VREG Internal Regulator Supply Bias Voltage for the ADP1874/ADP1875 Controller (Includes the Output Gate Drivers). A
bypass capacitor of 1 µF directly from this pin to PGND and a 0.1 µF across VREG and GND are recommended.
8 VREG_IN Input to the Internal LDO. Tie this pin directly to Pin 7 (VREG).
9 TRACK Tracking Input. If the tracking function is not used, it is recommended to connect TRACK to VREG through a resistor
higher than 1 MΩ or simply connect TRACK between 0.7 V and 2 V to reduce the bias current going into the pin.
10 SS Soft Start Input. Connect an external capacitor to GND to program the soft start period. Capacitance value of 10 nF for
every 1 ms of soft start delay.
11
PGOOD
Open-Drain Power Good Output. Sinks current when FB is out of regulation or during thermal shutdown. Connect a
3 kΩ resistor between PGOOD and VREG. Leave unconnected if not used.
12 DRVL Drive Output for the External Lower Side, N-Channel MOSFET. This pin also serves as the current-sense gain setting pin (see
Figure 69).
13 PGND Power GND. Ground for the lower side gate driver and lower side, N-channel MOSFET.
14
DRVH
Drive Output for the External Upper Side, N-Channel MOSFET.
15 SW Switch Node Connection.
16 BST Bootstrap for the Upper Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected between VREG and
BST. A capacitor from BST to SW is required. An external Schottky diode can also be connected between VREG and BST for
increased gate drive capability.