Datasheet
ADP1874/ADP1875 Data Sheet
Rev. A | Page 36 of 44
LAYOUT CONSIDERATIONS
The performance of a dc-to-dc converter depends highly on how
the voltage and current paths are configured on the printed circuit
board (PCB). Optimizing the placement of sensitive analog and
power components is essential to minimize output ripple, maintain
tight regulation specifications, and reduce PWM jitter and
electromagnetic interference.
Figure 90 shows the schematic of a typical ADP1874/ADP1875
used for a high current application. Blue traces denote high current
pathways. VIN, PGND, and V
OUT
traces should be wide and
possibly replicated, descending down into the multiple layers.
Vias should populate, mainly around the positive and negative
terminals of the input and output capacitors, alongside the source
of Q1/Q2, the drain of Q3/Q4, and the inductor.
10kΩ
V
REG
MURATA: (HIGH VOLTAGE INPUT CAPACITORS)
22µF, 25V, X7R, 1210 GRM32ER71E226KE15L
PANASONIC: (OUTPUT CAPACITORS)
270µF, SP-SERIES, 4V, 7mΩ EEFUE0G271LR
INFINEON MOSFETs:
BSC042N03MS G (LOWER SIDE)
BSC080N03MS G (UPPER SIDE)
WÜRTH INDUCTORS:
1µH, 3.8mΩ, 16A 7443552100
Q3 Q4
Q1 Q2
HIGH VOLTAGE INPUT
V
IN
= 12V
C
BST
100nF
V
OUT
= 1.8V, 15A
C3
22µF
C4
22µF
C5
22µF
C6
22µF
C7
22µF
C8
N/A
C9
N/A
C23
270µF
+
C22
270µF
+
C21
270µF
+
C20
270µF
+
C27
N/A
C14 TO C19
N/A
+
C26
N/A
+
C25
N/A
+
C24
N/A
+
1.0µH
R
SNB
2Ω
C
SNB
1.5nF
R
TOP
2kΩ
R7 10kΩ
R
BOT
1kΩ
V
OUT
1
VIN
16
BST
2
COMP
15
SW
3
EN
14
DRVH
5
GND
12
DRVL
ADP1874/
ADP1875
C
C
430pF
C
PAR
53pF
R
C
57kΩ
C1
1µF
C
VIN
22µF
C2
0.1µF
JP3
R
RES
100kΩ
4
FB
13
PGND
6
RES
11
PGOOD
7
VREG
10
SS
8
VREG_IN
9
TRACK
5kΩ
V
REG
C
SS
34nF
V
REG
09347-081
Figure 90. ADP1874/ADP1875 High Current Evaluation Board Schematic (Blue Traces Indicate High Current Paths)
09347-092
INPUT CAPACITORS
ARE MOUNTED CLOSE
TO DRAIN OF Q1/Q2
AND SOURCE OF Q3/Q4
SEPARATE ANALOG
GROUND PLANE FOR
COMPENSATION AND
FEEDBACK RESISTORS
SENSITIVE ANALOG
COMPONENTS
LOCATED FAR
FROM NOISY
POWER SECTION
OUTPUT
CAPACITORS
ARE MOUNTED
AT RIGHTMOST
AREA OF
EVALUATION
BOARD
Figure 91. Overall Layout of the ADP1874/ADP1875 High Current Evaluation Board