Datasheet

Data Sheet ADP1872/ADP1873
Rev. B | Page 33 of 40
08297-082
OUTPUT CAPACITORS
ARE MOUNTED ON THE
RIGHTMOST AREA OF
THE EVB, WRAPPING
BACK AROUND TO THE
MAIN POWER GROUND
PLANE, WHERE IT MEETS
WITH THE NEGATIVE
TERMINALS OF THE
INPUT CAPACITORS
INPUT CAPACITORS
ARE MOUNTED CLOSE
TO DRAIN OF Q1/Q2
AND SOURCE OF Q3/Q4.
BYPASS POWER CAPACITOR (C1)
FOR VREG BIAS DECOUPLING
AND HIGH FREQUENCY
CAPACITOR (C2) AS CLOSE AS
POSSIBLE TO THE IC.
SENSITIVE ANALOG
COMPONENTS
LOCATED FAR
FROM THE NOISY
POWER SECTION.
SEPARATE ANALOG GROUND
PLANE FOR THE ANALOG
COMPONENTS (THAT IS,
COMPENSATION AND
FEEDBACK RESISTORS).
Figure 83. Overall Layout of the ADP1872 High Current Evaluation Board
SW